Speed Example need the design run at 78MHZ Danny Mok Altera HK FAE Copyright 1997 Altera Corporation (amok@altera.com) 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Speed Example I need the design run at 78MHZ Danny Mok Altera HK FAE (dmok@altera.com)
Design Requirement a The design need to run at 78Mhz or above All the pin has been locked down, you can not changed any lO pin a You are allowed to modify the circuit as far as the functional does not changed You can use any design entry method Graphic AHDL VHDL anything you like Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Design Requirement ◼ The design need to run at 78Mhz or above ◼ All the pin has been locked down, you can not changed any I/O pin ◼ You are allowed to modify the circuit as far as the functional does not changed ◼ You can use any design entry method – Graphic – AHDL – VHDL – anything you like
Let us look at the design first wts wttc 5 bBRA Copyright 1997 Altera Corporation All the I/O Pin can not be changed 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Let us look at the design first All the I/O PIN can not be changed
Trial Run -What is the speed I can get Timing Analyzer 回区 Registered Performance God, I only get 24.63Mhz, but I need 78Mhz Clock: clockin(10 paths) Source: squ. 38: 54.Q Destination: squ. 38/9odf: 551:3.Q 78.2463=53.37Mhz Can i make it ????? MHz Clock period: 40.6ns Frequency: 24.63MH St tart Stop List Paths bBRA Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Trial Run -- What is the speed I can get God, I only get 24.63Mhz, but I need 78Mhz 78 - 24.63 = 53.37Mhz Can I make it ??????
Step 1-why it is so slow? sI Messages- Timing Analyzer 口区 Info: Delay path from"squ: 38: 54'to'squ 38 odf: 551: 3: 38 3ns (Clock period: 406ns Info: Delay path from squ: 38: 54to ' squ: 38 odf: 55: 1: 383ns (Clock period: 406ns Info: Delay path from squ: 38: 54to 'squ: 389odf: 55: 9: 382ns(Clock period: 405ns Info: Delay path from squ: 38: 54to squ: 38 9odf: 55: 8: 382ns [Clock period: 405ns Info: Delay path from squ: 38 54to ' squ: 38 odf: 55: 5: 381ns [Clock period: 404ns This is the Info: Delay path from squ 38: 54 squ: 38 odf: 55:2 .381ns (Clock period: 40 4ns delay path which Info: Delay path from squ: 38 :54 to squ: 38 9odf: 55: 7:379ns (Clock period: 402ns) cause it run at Info: Delay path from squ: 38 54 to 'squ: 38 odf:55 4: 379ns (Clock period: 402ns Info: Delay path from'Isqu: 38 54to'Isqu: 38 9odf: 55 6: 37.8ns (Clock period: 40.Ins) so slow Info Delay path from'Isqu: 38 40 Isqu: 38 odf: 55: 3: 373ns (Clock period: 396ns) We must locate this path first before we can do anything 4 Message b 1 of 10 Locate in Floorplan Editor Help on Message Locate↓0of10 1.往A籍 bBRA Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Step 1 - why it is so slow ? This is the delay path which cause it run at so slow. We must locate this path first before we can do anything
Step 2 -look at the circuit The path look like this is the logic which having a large dela owbip(LC4_J35 ROWFP Cs[9. QC..王3 CLEAR bBRA Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Step 2 - look at the circuit The path look like this is the logic which having a large delay
Step 3 -look at the module BEGIN IF clear'1 THEN cntcscscscscscscscscsCS<=000000000 END CASE Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Step 3 - look at the module BEGIN IF clear='1' THEN cnt cscscscscscscscscscs<="000000000"; END CASE; DFF OUTPUT DEPENDS ON THE COUNTER VALUE DFF Big combinational logic cause a big DELAY COUNTER DFF
Step 4-Modify the Source Code BEGIN IF clearI THEN cntcsnodecsnodecsnodecsnodecsnodecsnodecsnodecsnodecsnode<=000000000 END CASE Output depends on the END PROCESS. process(rowfp, csnode ADVANCE counter Add an extra dFe if (rowfp'event and rowtp=I') then value cs<= csnode- end if Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Step 4 - Modify the Source Code BEGIN IF clear='1' THEN cntcsnodecsnodecsnodecsnodecsnodecsnodecsnodecsnodecsnodecsnode<="000000000"; END CASE; END PROCESS; process(rowfp,csnode) begin if (rowfp'event and rowfp='1') then cs <= csnode; end if; end process; DFF COUNTER DFF OUTPUT DEPENDS ON THE ADVANCE COUNTER VALUE DFF DFF Add an extra DFF Output depends on the ADVANCEcounter value
Compare the Two source code BEGIN BEGIN IF clearI THEN IF clear1 THEN cntcsnodecsnodecsnodecsnodecsnodecscsnodecscscsnodecscsnodecscscscscsCS<=000000000 end正f Copyright+合 corporation 9/12/97 Functional exactly the same
Copyright © 1997 Altera Corporation 9/12/97 Compare the Two source code BEGIN IF clear='1' THEN cnt cscscscscscscscscscscsnodecsnodecsnodecsnodecsnodecsnodecsnodecsnodecsnodecsnode<="000000000"; END CASE; END PROCESS; process(rowfp,csnode) begin if (rowfp'event and rowfp='1') then cs <= csnode; end if; end process; Functional exactly the same
Compare the stand alone module 口区 区 Registered Performance Registered Performance Clock: 2Q (10 paths) ource Source: lclum9. 8)cnt3. Q Destination: " 67.0 Destination: lclum9. 8cnt3Q 160 Clock period 9 Frequency: 107. 52MHz Clock period: 8.7ns Frequency: 114.94MHz Start Stop List Paths Start List Paths bBRA Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Compare the stand alone module
