《计算机英语》Compilation is too Long

If you were a If you were Altera Software Engineer, what shall you do? Graphic Entry H Graphic Compiler H Graphic processor VHDL Entry H VHDL Compiler H VHDL processor Fitting

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If you were If you were Altera Software Engineer, what shall you do? Graphic Entry H Graphic Compiler H Graphic processor VHDL Entry VHDL Compiler H VHDL processor Fitting AHDL Entry AHDL Compiler AHDL processor EDIF Entry EDIF Compiler H EDIF processor Need different Processor for different Design Entry Copyright 1997 Altera Corporation 2/22/2021P favara

Copyright © 1997 Altera Corporation 2/22/2021 P.3 If you were ◼ If you were Altera Software Engineer, what shall you do ? Graphic Entry Graphic Compiler Fitting VHDL Entry VHDL Compiler Graphic processor VHDL processor AHDL Entry EDIF Entry AHDL Compiler EDIF Compiler AHDL processor EDIF processor Need different Processor for different Design Entry

The other better solution Graphic Entry Graphic Compiler VHDL Entry VHDL Compiler Altera nterna Fitting Datab AHDL Entry AHDL Compiler Structurel EDIF Entry EDIF Compiler /AbsRA 2/22/2021P4 favara

Copyright © 1997 Altera Corporation 2/22/2021 P.4 The Other better solution Graphic Entry Graphic Compiler VHDL Entry VHDL Compiler AHDL Entry EDIF Entry AHDL Compiler EDIF Compiler Altera Internal Database Structure Fitting

Altera Max+Plus ll compiler 口区 Compiler Databas Logi Timing Netlist Builder Synthesizer Partitioner Fitter SNF Assembler Extractor Extractor Stop Convert to Partition your Get the device Altera internal whole design timing parameter Data Base into couple for Real time Structure chips Simulation Involve all different Generate the ogIc kind of Optimize Fit your design Program File om pll within altera to program the e.g. AHDL, e.g. Hierarchy Synthesis device device One-Hot State Machine VHDL, Graphic e.g. SOF, POF Carry/Cascade Chain e.g. Pin lock EDIF Implement in EAB Multi-level Synthesis Copyright 1997 Altera Corporation Clique /AbsRA 2/22/2021P Timing parameter favara

Copyright © 1997 Altera Corporation 2/22/2021 P.5 Altera Max+Plus II Compiler Involve all different kind of Compiler e.g. AHDL, VHDL, Graphic EDIF….. Convert to Altera Internal DataBase Structure Logic Optimize e.g. Hierarchy Synthesis One-Hot State Machine Carry/Cascade Chain Multi-level Synthesis…. Partition your whole design into couple chips Fit your design within Altera device e.g. Pin lock, Implement in EAB Clique, Timing parameter Get the device timing parameter for Real time Simulation Generate the Program File to program the device e.g. SOF, POF

How many time spend on each Module Compilation Times Compiler Netlist Extractor 90:99:04 Database builder 90:86:4 Logic Synthesize 00:6:18 Most of the time spend on Partitioner 90:6:5 thiS TWo modules Fitter 60: 60:18 Timing SNF Extractor 90:08:02 Assembler 0:98:2 Total time 00:06:37 Shange mths Copyright 1997 Altera Corporation 2/22/2021P favara

What you can do for Netlist/database Part Compiler Database Smart/Total Compiler can help Netlist Builder Smart Compiler Extractor if this is first time compilation save the database result for future compilation Processing Interfaces Assign Options Design Doctor if this is second compilation without modify of Design Doctor Settings the design, this step will be skipped Functional SNF Extractor Total compiler y Timing SNF Extract Optimize Timing SNIF no matter the design has been modified or not ed SNF Extractor the system will go through this step again Fitter Settings Report File Settings Turn on Smart Compiler Generate AHDL TDO File first time need longer than Total Compiler need more harddisk space to store the database Total recompile nformation Preserve All Node Name Synonyms subsequence will need LESS TIME than Total Compiler Copyright 1997 Altera Corporation 2/22/2021P7 favara

Copyright © 1997 Altera Corporation 2/22/2021 P.7 What you can do for Netlist/Database Part ◼ Smart/Total Compiler can help – Smart Compiler • if this is first time compilation, save the database result for future compilation • if this is second compilation without modify of the design, this step will be skipped – Total Compiler • no matter the design has been modified or not, the system will go through this step again ◼ Turn on Smart Compiler – first time need longer than Total Compiler – need more harddisk space to store the database information – subsequence will need LESS TIME than Total Compiler

What you can do for Logic Synthesiser Part Logic a Only turn on the option which is ueeful Synthesizer turn on XOR Synthesis under FE, useless turn on Parallel Expanders t fLEX is useless Project Name ir: Untitedl. di a If you design file is EDIRM)ich is already lobal Project Synthesis Style 1 oPtimize WYSIWYG Optimize by Synopsys) you can min tit. pend on the Max+ Plus ll Logic MAX Device Synthesis Options Synthesize O Mult- Level Synthesis for HAX 5000/7000 Devices s eithe WYSIWYG rOne-Hot Stale Machine Encoding don't forget to turn on Cascade/Carry 「 Automatic Register Packing Chain for flex device AUtomatic Open-Drain Pir T Automatic Implement in EAB don't forget to turn on the Parallel Expanders for MAX device you can also let Max+ Plus l does further Logic ptimize for you /AbsRA 2/22/2021P favara

Copyright © 1997 Altera Corporation 2/22/2021 P.8 What you can do for Logic Synthesiser Part ◼ Only turn on the Option which is useful – turn on XOR Synthesis under FLEX is useless – turn on Parallel Expanders under FLEX is useless ◼ If you design file is EDIF which is already Optimize by Synopsys – you can min. time spend on the Max+Plus II Logic Synthesizer • Select the WYSIWYG – don’t forget to turn on Cascade/Carry Chain for FLEX device – don’t forget to turn on the Parallel Expanders for MAX device – you can also let Max+Plus II does further Logic Optimize for you

EDIF file input with different Synthesis Style Registered Performance Compilation Times Clock: LCLK:(10 patha) ource"store Compiler Netlist Extractor g6:8:2 ase Bu 96:60:01 ogic Syn Partitioner g:60:83 r1。 96:00:04 Timing SNF Extractor 6:8:g2 Assembler 96::01 Start 」L=Pat=」 Total Time 96:0:15 Timing Analy之∈ Registered Performance Clock: CLK (10 paths) Compilation Times Destination stegea_1-Q Compiler Netlist Extractor 6:8目:g2 Logic Synthesizer Partitioner 98:08:83 Fitter Clock period: 15. 5ns Timing sNF Extractor g:目g:g2 Frequency: 64.51MH2 bler 6:0:61 Total Time g0:0:22 start Stop List Paths Copyright 1997 Altera Corporation 2/22/2021P favara

What you can do for Partitioner Part a If your design does not need to partition to Partitioner different chip, this only takes couple seconds a If your design need to partition to different chip Max+ Plus II automatic partitioning will take onger time You can save this time by doing Manual Partition by either use Assign Device Option Physically split your design to different design file Copyright 1997 Altera Corporation 2/22/2021P10 favara

Copyright © 1997 Altera Corporation 2/22/2021 P.10 What you can do for Partitioner Part ◼ If your design does not need to partition to different chip, this only takes couple seconds ◼ If your design need to partition to different chip, – Max+Plus II automatic partitioning will take longer time – You can save this time by doing Manual Partition by either • use Assign Device Option • Physically split your design to different design file

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