Three Routing Possibility 了口回mmAm □区 Routin g 3 Registered Performance Clock: ck (1 paths) FasttrackM Interconnect Source:: 1.0 Destination:: 2.0 150 日日 Clock period: 7.3ns Frequency: 1 2 Maximum delay Start Stop ist Paths LC-> ROW->COL - LC Copyright 1997 Altera Corporation 2/22/2021P favaraCopyright © 1997 Altera Corporation 2/22/2021 P.6 Three Routing Possibility FastTrack™ Interconnect Maximum Delay LC -> ROW -> COL -> LC Routing 3