Balancing Operators (Cont.) Data in register register register register h(o) h(1) h(2) h(3) Data out Use Parenthesis to Define Logic Groupings Increases Performance Utilization >Balances Delay from All Inputs to Output Circuit Functionality Unchanged 2021/1/13 ASIC Design,by Yan Bo 12ASIC Design, by Yan Bo Balancing Operators （Cont.） 2021/1/13 12 Use Parenthesis to Define Logic Groupings ➢ Increases Performance & Utilization ➢ Balances Delay from All Inputs to Output ➢ Circuit Functionality Unchanged