1530 半导体学报 第26卷 real,but not complex,as in negative variation. variation,for the stability concerns.The simulation However,large positive variation is not desired due and measurement results well verify the analysis to the small ripple caused by under-damping.The and methods with the example. measured channel switching responses of control voltage are shown in Fig.8.To verify the variation Acknowledge The authors would like to thank Li factor analysis,VCO operates at 1GHz with gain Fuxiao,Chen Zai,and Wang Xiuying for chip pack- smaller than 30MHz/V.Normally,the charge age and testing.We would also like to thank Liu pump current is trimmed to the designed value by Chenbo,Yi Wei,and Jiang Qifeng of Shanghai Re- the external reference Ief,when no adjustment is search Center for Integrated Circuit Design,China, required and the response of the loop is stable be- for the support of MPW service. cause of the variation margin.After the external reference current is set 60%smaller than designed References value,the extra negative variation of charge pump current is introduced and the loop goes to under- [1]Wilson W B.Moon U K.Lakshmikumar K R.et al.A CMOS damping.With the double adjustment of variation self-calibrating frequency synthesizer.IEEE J Solid-State Cir- cuits,2000,35(10):1437 factor,the switching response is compensated and [2 Rategh H R.Samavati H.Lee T H.A CMOS frequency syn- more stable than that without adjustment. thesizer with an injection-locked frequency divider for a 5- GHz wireless LAN receiver.IEEE J Solid-State Circuits. 0.4/.w/adjustment 0.4/w/o.adjustment 2000.35(5):780 1.00025GHz 3 Colleran D M.Portmann C.Hassibi A.et al.Optimization of phase-locked loop circuits via geometric programming.Custom Integrated Circuits Conference.2003:377 [4]Craninckx J.Steyaert M.A fully integrated CMOS DCS-1800 frequency synthesizer.IEEE J Solid-State Circuits,1998.33 1.00000 GHz (12):2054 [5]Terrovitis M.Mack M.Singh K.et al.A 3.2 to 4GHz 0.25gm 50μs/div CMOS frequency synthesizer for IEEE 802.11a/b/g WLAN. IEEE International Solid-State Circuits Conference.2004:98 Fig.8 Channel switching responses of control voltage [6]Zhao Hui.Ren Junyan.Zhang Qianling.A 900MHz CMOS for variation factor adjustment test,with 60%extra PLL/frequency synthesizer initialization circuit.Chinese Jour- current reduction nal of Semiconductors.2003.24(12):1244 [7]Larsson P.A 2-1600-MHz CMOS clock recovery PLL with 5 Conclusion low-Va capability.IEEE J Solid-State Circuits.1999.34(12): 1951 [8]Gardner F M.Charge-pump phase-lock loops.IEEE Trans The complete closed-loop third-order s-domain Commun,1980,28(11):1849 model is analyzed.Based on the analysis,a proce- [9]Hanumolu P K.Casper B.Mooney R.et al.Analysis of dure for parameter design is proposed for the fre- charge-pump phase-locked loops.IEEE Trans Circuits Sys- quency synthesizer,and the margin for the total pa- tems-I:Regular Papers.2004.51(9):1665 [10]Hein J P,Scott J W.z-domain model for discrete-time PLL's. rameters'PVT variation is quantitatively ana- IEEE Trans Circuits and Systems,1988,35(11):1393 lyzed.It is suggested that the damping factor o=1 [11]Razavi B.RF microelectronics.Prentice Hall Press.2000 is a good start to variation toleration.For more [12]Lin Li.Tee L.Gray P R.A 1.4GHz difference low-noise variation,a double-half adjustable current cell in CMOS frequency synthesizer using a wideband PLL architec- ture.IEEE International Solid-State Circuits Conference, the charge pump is proposed to compensate the 2000:204 variation for the stability.Additionally,a novel [13]Tang Zhangwen.LC voltage-controlled oscillators.PhD Dis- VCO with linear gain is adopted to limit the total sertion.Fudan University.2004半 导 体 学 报 第!#卷 D=79$KNF?EF:E6M9=\$7<8? ?=J7F8X= X7D87F8E?> IE@=X=D$97DJ=ME<8F8X=X7D87F8E?8<?EFR=<8D=RRN= FEFG=<6799D8MM9=:7N<=RKLN?R=D0R76M8?J>/G= 6=7<ND=R:G7??=9<@8F:G8?JD=<ME?<=<EH:E?FDE9 XE9F7J=7D=<GE@?8?U8J>&>/EX=D8HLFG=X7D87F8E? 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