MC14553B UNITS CLOCK wuuuuuuu wuuu uuuuuuuuu UNTS0几m∏「L“ LLILLLLLI广tnLL UNITS Q2 TENS Q0 TENS Q3 UP AT 80 UP AT 980 HUNDREDS QO HUNDREDS 03 DISABLE L(DISABLES CLOCK WHEN HIGH) UP AT 800 OVERFLOW OSCILLATOR DIGIT SELECT 1 UNITS DIGIT SELECT 2 DIGIT SELECT 3 LHUNDREDS厂 Figure 2. 3-Digit Counter Timing Diagram(Reference Figure 4) 169 VDD ERATOR Foc a GENER *+tpHL D51 OVERFLOW GENERATOR Q3 -trem LATCH GENERATOI GENERATOR MASTER RESET 50% Figure 3. Switching Time Test Circuits and Waveforms httpllonsemi.comMC14553B http://onsemi.com 5 Figure 2. 3–Digit Counter Timing Diagram (Reference Figure 4) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 899 900 901 990 991 992 993 994 995 996 997 998 999 1000 UNITS CLOCK UNITS Q0 UNITS Q1 UNITS Q2 UNITS Q3 TENS CLOCK TENS Q0 TENS Q3 HUNDREDS CLOCK HUNDREDS Q0 HUNDREDS Q3 DISABLE OVERFLOW MASTER RESET SCAN OSCILLATOR DIGIT SELECT 1 DIGIT SELECT 2 DIGIT SELECT 3 UP AT 80 UP AT 980 UP AT 800 (DISABLES CLOCK WHEN HIGH) UNITS TENS HUNDREDS PULSE GENERATOR (a) 16 VDD Q3 Q2 Q1 Q0 O.F. DS1 DS2 DS3 8 VSS C LE DIS MR CL CL CL CL CL GENERATOR 1 (b) VDD Q3 Q2 Q1 Q0 O.F. DS1 DS2 DS3 VSS C LE MR DIS CL CL CL CL CL GENERATOR 2 GENERATOR 3 20 ns 20 ns 90% 10% tPLH tPHL 50% 50% tTHL tTLH 10% 90% 50% 1/fcl tWL(cl) 999 1000 tTLH 50% OVERFLOW BCD OUT CLOCK 90% 10% trem tPHL, tPLH 50% 50% 50% tWH(R) tsu tPHL MASTER RESET BCD OUT LATCH ENABLE CLOCK Figure 3. Switching Time Test Circuits and Waveforms tsu tPHL