Mc14553B 3- Digit BCD C。 unter ON The MC14553B 3-digit BCD counter consists of 3 negative edge riggered BCD counters that are cascaded synchronously. A quad latch at the output of each counter permits storage of any given count. The information is then time division multiplexed, providing one BCD oN Semiconductor number or digit at a time. Digit select outputs provide display control http:/lonsemi.com All outputs are TTL compatible which drives the multiplexer output selector equency scanning clock This device is used in instrumentation counters, clock displays MARKING digital panel meters, and as a building block for general logic pplications PDIP-16 TTL Compatible Outputs P SUFFIX MC14553BCP · On-Chip oscillator CASE 648 AWLYYW Clock Disable Input Pulse Shaping Permits Very Slow Rise Times on Input Clock Output Latches SOIC-16 4553B Master Reset DW SUFFIX CASE 751G MAXIMUM RATINGS (Voltages Referenced to Vss)(Note 1.) Symbol Parameter Value Unit Assembly Location WL, L Wafer Lot VDD DC Supply Voltage Range 0.5to+18.0 Vin, Vout Input or Output Voltage Range -0.5 to VoD +0.5 V W. w Work Week (DC or Transient) ±10 (DC or Transient) per Pin ORDERING INFORMATION Output Current Pin MC14553BCP PDIP-16 25/Rail per Package( Note 2.) MC1453800-1647R T Ambient Temperature Range -55to+125 C Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating Plastic"P and D/DW Packages: -7.0 mW/C From 65C To 125.C static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this pedance circuit For proper operation, Vin and vout should be constrained to the range Vss s(Vin or Vout)s VDD. Unused inputs must always be tied to an appropriate logic voltage level(e. g either Vss or VoD). Unused outputs must be left open. e Semiconductor Components Industries, LLC, 2001 on Order Number February, 2001-Rev 5
Semiconductor Components Industries, LLC, 2001 February, 2001 – Rev. 5 1 Publication Order Number: MC14553B/D MC14553B 3-Digit BCD Counter The MC14553B 3–digit BCD counter consists of 3 negative edge triggered BCD counters that are cascaded synchronously. A quad latch at the output of each counter permits storage of any given count. The information is then time division multiplexed, providing one BCD number or digit at a time. Digit select outputs provide display control. All outputs are TTL compatible. An on–chip oscillator provides the low–frequency scanning clock which drives the multiplexer output selector. This device is used in instrumentation counters, clock displays, digital panel meters, and as a building block for general logic applications. • TTL Compatible Outputs • On–Chip Oscillator • Cascadable • Clock Disable Input • Pulse Shaping Permits Very Slow Rise Times on Input Clock • Output Latches • Master Reset MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) Symbol Parameter Value Unit VDD DC Supply Voltage Range –0.5 to +18.0 V Vin, Vout Input or Output Voltage Range (DC or Transient) –0.5 to VDD + 0.5 V Iin Input Current (DC or Transient) per Pin ±10 mA Iout Output Current (DC or Transient) per Pin +20 mA PD Power Dissipation, per Package (Note 2.) 500 mW TA Ambient Temperature Range –55 to +125 °C Tstg Storage Temperature Range –65 to +150 °C TL Lead Temperature (8–Second Soldering) 260 °C 1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. http://onsemi.com A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week Device Package Shipping ORDERING INFORMATION MC14553BCP PDIP–16 25/Rail MC14553BDW SOIC–16 47/Rail MARKING DIAGRAMS 1 16 PDIP–16 P SUFFIX CASE 648 MC14553BCP AWLYYWW SOIC–16 DW SUFFIX CASE 751G 1 16 14553B AWLYYWW
MC14553B IA CIB Q1H07 D St D33 VoD= PIN 16 Figure 1. Block Diagram TRUTH TABLE Master Reset Clock Disable Outputs 000 0 No Change 0 1 X No Change No Change 000 No Change Q0=Q1=Q2=Q3=0 X= Dont Care httpllonsemi.com
MC14553B http://onsemi.com 2 Figure 1. Block Diagram 12 10 11 13 9 7 6 5 14 2 1 15 VDD = PIN 16 VSS = PIN 8 4 3 CLOCK LE DIS MR Q0 Q1 Q2 Q3 O.F. DS1 DS2 DS3 CIA CIB TRUTH TABLE Inputs Master Reset Clock Disable LE Outputs 0 0 0 No Change 0 0 0 Advance 0 X 1 X No Change 0 1 0 Advance 0 1 0 No Change 0 0 X X No Change 0 X X Latched 0 X X 1 Latched 1 X X 0 Q0 = Q1 = Q2 = Q3 = 0 X = Don’t Care
MC14553B ELECTRICAL CHARACTERISTICS (Voltages Referenced to Vss) 25°c 125°c Characteristic Vdc Min Max Min (Note 3. Max MinMaxUnit Output Voltage ” Level 0.05 000 0.05 0.05Vdc 10 0.05 0.05 0.05 0.05 1"Level VoH 5.0 95 4.95 Vdc Vin=o or vi DD 10 9.95 9.95 9.95 1514.95 14.95 14.95 Input Voltage Vdc o=450r0.5vdc) No= 9.0 or 1.0 Vdc) 3.0 3.0 No= 13.5 or 1.5 Vdc) 15 4.0 0525万 4.0 4.0 1" Levelⅵ Vdc o=0.5045vdc) 3.5 1070 5.50 lo=1.5 or 13.5 Vdc) 15 Output Drive Current mAdc (oH =9.5 Vdc) 0.62 05-09 NoH =13.5 Vdc) 4.6 Vdc) Source 0.51 0.88 mAdc 5 Vdc) Outputs (VoL =0.4 Vdc) (VoL =1.5 Vdc) (VoL =0.4 Vdc) Sink-Other mAdc Outputs put Current ±0.1 ±000001±0.1 ±10uAdc put Capacitance p Quiescent Current 5.0 0.010 150 HAdc (Per Package 10 10 0.020 10 MR= V 0.030 600 50 IT =(0. 35 HA/kHz)+IDt (Dynamic plus Quiescent, 10 IT =(0. 85 HA/kHz)+IDt Per Package) 15 IT =(1.50 HA/kHz)f+IDD (CL =50 pF on all outputs, all buffers switching) 3. Data labelled"Typ" is not to be used f purposes but is intended as an indication of the ICs potential performance only at25°C 5. To calculate total supply current at load than 50 pF I(Cu=I(50 pF)+(CL-50)Vik where: IT is in uA(per package), CL in pF, V=(VDD-Vss)in volts, f in kHz is input frequency, and k= 0.004 httpllonsemi.com
MC14553B http://onsemi.com 3 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) – 55C 25C 125C Characteristic Symbol VDD Vdc Min Max Min Typ (Note 3.) Max Min Max Unit Output Voltage “0” Level Vin = VDD or 0 VOL 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0 0 0 0.05 0.05 0.05 — — — 0.05 0.05 0.05 Vdc “1” Level Vin = 0 or VDD VOH 5.0 10 15 4.95 9.95 14.95 — — — 4.95 9.95 14.95 5.0 10 15 — — — 4.95 9.95 14.95 — — — Vdc Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL 5.0 10 15 — — — 1.5 3.0 4.0 — — — 2.25 4.50 6.75 1.5 3.0 4.0 — — — 1.5 3.0 4.0 Vdc “1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) VIH 5.0 10 15 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — Vdc Output Drive Current (VOH = 4.6 Vdc) Source — (VOH = 9.5 Vdc) Pin 3 (VOH = 13.5 Vdc) IOH 5.0 10 15 – 0.25 – 0.62 – 1.8 — — — – 0.2 – 0.5 – 1.5 – 0.36 – 0.9 – 3.5 — — — –0.14 –0.35 –1.1 — — — mAdc (VOH = 4.6 Vdc) Source — (VOH = 9.5 Vdc) Other (VOH = 13.5 Vdc) Outputs 5.0 10 15 – 0.64 – 1.6 – 4.2 — — — – 0.51 – 1.3 – 3.4 – 0.88 – 2.25 – 8.8 — — — – 0.36 – 0.9 – 2.4 — — — mAdc (VOL = 0.4 Vdc) Sink — (VOL = 0.5 Vdc) Pin 3 (VOL = 1.5 Vdc) IOL 5.0 10 15 0.5 1.1 1.8 — — — 0.4 0.9 1.5 0.88 2.25 8.8 — — — 0.28 0.65 1.20 — — — mAdc (VOL = 0.4 Vdc) Sink — Other (VOL = 0.5 Vdc) Outputs (VOL = 1.5 Vdc) 5.0 10 15 3.0 6.0 18 — — — 2.5 5.0 15 4.0 8.0 20 — — — 1.6 3.5 10 — — — mAdc Input Current Iin 15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc Input Capacitance (Vin = 0) Cin — — — — 5.0 7.5 — — pF Quiescent Current (Per Package) MR = VDD IDD 5.0 10 15 — — — 5.0 10 20 — — — 0.010 0.020 0.030 5.0 10 20 — — — 150 300 600 µAdc Total Supply Current (Note 4., 5.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT 5.0 10 15 IT = (0.35 µA/kHz) f + IDD IT = (0.85 µA/kHz) f + IDD IT = (1.50 µA/kHz) f + IDD µAdc 3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 4. The formulas given are for the typical characteristics only at 25C. 5. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004
Mc14553B SWITCHING CHARACTERISTICS (Note 6. )(CL= 50 pF, TA=25C) Characteristic Figure Symbol (Note 7) Output Rise and Fall Time tTLH, tTHL=(1.5 ns/pF)CL+ 25 ns 100 tTLH, tTHL=(0.75 ns/pF)CL+ 12.5 TLH, tTHL=(0.55 ns/pF)CL+9.5ns Clock to BCD Out tPLH 500500500 900 1800 500 Clock to Overflow 1200 200 Reset to bcd out 1800 300 600 Clock to Latch Enable Setup Time 50 Master Reset to Latch Enable Setup Time 200 Removal Time Latch Enable to clock Clock pulse width twH(cl) 5505 150 Reset Pulse Width tWH(R) 00 Reset Removal Time 180 Input Clock Frequency 500 MHz 5 Input Clock Rise Time 550560 No Limit Disable. MR. Latch Enable 15 Rise and Fall Times 4.0 Scan Oscillator Frequency 15/C1 (C1 measured in uF) 4.2C1 7C1 6. The formulas given are for the typical characteristics only at 25C. 7. Data labelled"Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance httpllonsemi.com
MC14553B http://onsemi.com 4 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (Note 6.) (CL = 50 pF, TA = 25C) Characteristic Figure Symbol VDD Min Typ (Note 7.) Max Unit Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 2a tTLH, tTHL 5.0 10 15 — — — 100 50 40 200 100 80 ns Clock to BCD Out 2a tPLH, tPHL 5.0 10 15 — — — 900 500 200 1800 1000 400 ns Clock to Overflow 2a tPHL 5.0 10 15 — — — 600 400 200 1200 800 400 ns Reset to BCD Out 2b tPHL 5.0 10 15 — — — 900 500 300 1800 1000 600 ns Clock to Latch Enable Setup Time Master Reset to Latch Enable Setup Time 2b tsu 5.0 10 15 600 400 200 300 200 100 — — — ns Removal Time Latch Enable to Clock 2b trem 5.0 10 15 – 80 – 10 0 – 200 – 70 – 50 — — — ns Clock Pulse Width 2a tWH(cl) 5.0 10 15 550 200 150 275 100 75 — — — ns Reset Pulse Width 2b tWH(R) 5.0 10 15 1200 600 450 600 300 225 — — — ns Reset Removal Time — trem 5.0 10 15 – 80 0 20 – 180 – 50 – 30 — — — ns Input Clock Frequency 2a fcl 5.0 10 15 — — — 1.5 5.0 7.0 0.9 2.5 3.5 MHz Input Clock Rise Time 2b tTLH 5.0 10 15 No Limit ns Disable, MR, Latch Enable Rise and Fall Times — tTLH, tTHL 5.0 10 15 — — — — — — 15 5.0 4.0 µs Scan Oscillator Frequency (C1 measured in µF) 1 fosc 5.0 10 15 — — — 1.5/C1 4.2/C1 7.0/C1 — — — Hz 6. The formulas given are for the typical characteristics only at 25C. 7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance
MC14553B UNITS CLOCK wuuuuuuu wuuu uuuuuuuuu UNTS0几m∏「L“ LLILLLLLI广tnLL UNITS Q2 TENS Q0 TENS Q3 UP AT 80 UP AT 980 HUNDREDS QO HUNDREDS 03 DISABLE L(DISABLES CLOCK WHEN HIGH) UP AT 800 OVERFLOW OSCILLATOR DIGIT SELECT 1 UNITS DIGIT SELECT 2 DIGIT SELECT 3 LHUNDREDS厂 Figure 2. 3-Digit Counter Timing Diagram(Reference Figure 4) 169 VDD ERATOR Foc a GENER *+tpHL D51 OVERFLOW GENERATOR Q3 -trem LATCH GENERATOI GENERATOR MASTER RESET 50% Figure 3. Switching Time Test Circuits and Waveforms httpllonsemi.com
MC14553B http://onsemi.com 5 Figure 2. 3–Digit Counter Timing Diagram (Reference Figure 4) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 899 900 901 990 991 992 993 994 995 996 997 998 999 1000 UNITS CLOCK UNITS Q0 UNITS Q1 UNITS Q2 UNITS Q3 TENS CLOCK TENS Q0 TENS Q3 HUNDREDS CLOCK HUNDREDS Q0 HUNDREDS Q3 DISABLE OVERFLOW MASTER RESET SCAN OSCILLATOR DIGIT SELECT 1 DIGIT SELECT 2 DIGIT SELECT 3 UP AT 80 UP AT 980 UP AT 800 (DISABLES CLOCK WHEN HIGH) UNITS TENS HUNDREDS PULSE GENERATOR (a) 16 VDD Q3 Q2 Q1 Q0 O.F. DS1 DS2 DS3 8 VSS C LE DIS MR CL CL CL CL CL GENERATOR 1 (b) VDD Q3 Q2 Q1 Q0 O.F. DS1 DS2 DS3 VSS C LE MR DIS CL CL CL CL CL GENERATOR 2 GENERATOR 3 20 ns 20 ns 90% 10% tPLH tPHL 50% 50% tTHL tTLH 10% 90% 50% 1/fcl tWL(cl) 999 1000 tTLH 50% OVERFLOW BCD OUT CLOCK 90% 10% trem tPHL, tPLH 50% 50% 50% tWH(R) tsu tPHL MASTER RESET BCD OUT LATCH ENABLE CLOCK Figure 3. Switching Time Test Circuits and Waveforms tsu tPHL
MC14553B OPERATING CHARACTERISTICS The MC14553B three-digit counter. shown in Figure 4 The Master Reset input, when taken high, initializes the consists of three negative edge-triggered BCD counters three BCD counters and the multiplexer scanning circuit which are cascaded in a synchronous fashion. a quad latch While master Reset is high the digit scanner is set to digit at the output of each of the three BCD counters permits one, but all three digit select outputs are disabled to prolong storage of any given count. The three sets of BCD outputs display life, and the scan oscillator is inhibited. The Disable (active high), after going through the latches, are time input, when high, prevents the input clock from reaching the division multiplexed, providing one BCD number or digit at counters, while still retaining the last count. a pulse shaping a time. Digit select outputs(active low)are provided for circuit at the clock input permits the counters to continue display control. All outputs are TTL compatible operating on input pulses with very slow rise times An on-chip oscillator provides the low frequency Information present in the counters when the latch input scanning clock which drives the multiplexer output selector. goes high, will be stored in the latches and will be retained The frequency of the oscillator can be controlled extemally while the latch input is high, independent of other inputs by a capacitor between pins 3 and 4, or it can be overridden Information can be recovered from the latches after the during the entire reset cycle Latch Enable remains high and driven with an external clock at pin 4. Multiple devices counters have been reset can be cascaded using the overflow output, which provides ne pulse for every 1000 counts. LATCH ENABLE SCAN PULSE OSCILLATOR3。 C1GENERATOR CLOCK 12 R SCANNER PULSE QUAD SHAPER LATCH UNITS MULTIPLEXER QUAD LATCH TENS HUNDREDS (LSD)DIGIT SELECT (M OVERFLOW (ACTIVE LOW) ACTIVE HIGH Figure 4. Expanded Block Diagram httpllonsemi.com
MC14553B http://onsemi.com 6 OPERATING CHARACTERISTICS The MC14553B three–digit counter, shown in Figure 4, consists of three negative edge–triggered BCD counters which are cascaded in a synchronous fashion. A quad latch at the output of each of the three BCD counters permits storage of any given count. The three sets of BCD outputs (active high), after going through the latches, are time division multiplexed, providing one BCD number or digit at a time. Digit select outputs (active low) are provided for display control. All outputs are TTL compatible. An on–chip oscillator provides the low frequency scanning clock which drives the multiplexer output selector. The frequency of the oscillator can be controlled externally by a capacitor between pins 3 and 4, or it can be overridden and driven with an external clock at pin 4. Multiple devices can be cascaded using the overflow output, which provides one pulse for every 1000 counts. The Master Reset input, when taken high, initializes the three BCD counters and the multiplexer scanning circuit. While Master Reset is high the digit scanner is set to digit one; but all three digit select outputs are disabled to prolong display life, and the scan oscillator is inhibited. The Disable input, when high, prevents the input clock from reaching the counters, while still retaining the last count. A pulse shaping circuit at the clock input permits the counters to continue operating on input pulses with very slow rise times. Information present in the counters when the latch input goes high, will be stored in the latches and will be retained while the latch input is high, independent of other inputs. Information can be recovered from the latches after the counters have been reset if Latch Enable remains high during the entire reset cycle. Figure 4. Expanded Block Diagram PULSE SHAPER CLOCK 12 11 DISABLE (ACTIVE HIGH) C R Q0 Q1 Q2 Q3 ÷10 UNITS C R Q0 Q1 Q2 Q3 ÷10 TENS C R Q0 Q1 Q2 ÷10 Q3 HUNDREDS 10 LATCH ENABLE QUAD LATCH QUAD LATCH QUAD LATCH R R SCAN OSCILLATOR SCANNER PULSE GENERATOR C1 4 3 C1A C1B MULTIPLEXER 9 7 6 5 Q0 Q1 Q2 Q3 BCD OUTPUTS (ACTIVE HIGH) 13 14 2 1 15 MR (ACTIVE HIGH) OVERFLOW DS1 DS2 DS3 (LSD) DIGIT SELECT (MSD) (ACTIVE LOW)
STROBE CLOCK-12dcLK Mc14553B C1B Mc14543B DMc145438 DISPLAYS ARE LOW CURREN NT LEDS MSD
MC14553B http://onsemi.com 7 Figure 5. Six–Digit Display VDD STROBE RESET CLOCK INPUT 10 13 5 6 7 9 15 1 2 14 3 4 12 11 CLK DIS Q3 Q2 Q1 Q0 DS3 DS2 DS1 C1A C1B O.F. µ 0.001 F 5 3 2 4 6 1 7 A B C D Ph LD BI a b c d e f g 9 10 11 12 13 15 14 MC14543B LSD VDD DISPLAYS ARE LOW CURRENT LEDs (I peak < 10 mA PER SEGMENT) MSD VDD 5 3 2 4 6 1 7 A B C D Ph LD BI a b c d e f g 9 10 11 12 13 15 14 MC14543B 10 13 5 6 7 9 15 1 2 14 3 4 12 11 CLK DIS Q3 Q2 Q1 Q0 DS3 DS2 DS1 C1A C1B O.F. MC14553B MC14553B LE MR LE MR
MC14553B CKAGE DIMENSIONS PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 山凸血凸凸 ISSUE R 1. DIMENSIONING AND TOLERANCING PER ANSI DT INCLUDE MOLD FLASH 只只因点 0500A回 5020004051101 http://onsemi.com
MC14553B http://onsemi.com 8 PACKAGE DIMENSIONS PDIP–16 P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– B F C S H G D J L M 16 PL SEATING 1 8 16 9 K PLANE –T– 0.25 (0.010) M T A M DIM MIN MAX MIN MAX INCHES MILLIMETERS A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01
MC14553B CKAGE DIMENSIONS SOIC-16 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G-03 ISSUE B INLCUDE MOLD B 由025ABd 14x e httpllonsemi.com
MC14553B http://onsemi.com 9 PACKAGE DIMENSIONS SOIC–16 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G–03 ISSUE B D 14X 16X B SEATING PLANE 0.25 B M T A S S 16 9 1 8 h X 45 M B M 0.25 H 8X E B A e A1 T A L C NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM MIN MAX MILLIMETERS A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 0 7
Mc14553B Notes httpllonsemi.com
MC14553B http://onsemi.com 10 Notes
