Philips Semiconductors Linear Products Timer NEISA/SE555/SE555C DESCRIPTION PIN CONFIGURATIONS The 555 monolithic timing circuit is a highly stable controller capable of producing accurate time delays, or oscillation In the time delay D, N, FE Packages mode of operation, the time is precisely controlled by one external resistor and capacitor. For a stable operation as an oscillator, the free running frequency and the duty cycle are both accurately controlled with two external resistors and one capacitor. The circuit TRIGGER 2 may be triggered and reset on falling waveforms, and the output 6 THRESHOLD structure can source or sink up to 200mA I5 CoNTROL VOLTAGE FEATURES F Package Turn-off time less than 2us Max operating frequency greater than 500kHz e Timing from microseconds to hours TRIGGER 3 12 DIsC e Adjustable duty cycle TTL compatible · Temperature stability of0.005%per°c TOP VIEW APPLICATIONS Sequential timing o Pulse width modulation ORDERING INFORMATION TEMPERATURE RANGE ORDER CODE 8-Pin Plastic Small Outline( SO) Package 0to+70°C NE5550 0174C 8-Pin Plastic Dual In-Line Package(DIP) 0to+70°C NE555N 8-Pin Plastic Dual In-Line Package(DIP) 40t+85°c 8-Pin Plastic Small Outline(SO) Package 40°cto+85°0 SA555D 0174C 8-Pin Hermetic Ceramic Dual In-Line Package(CERDIP) 8-Pin Plastic Dual In-Line Package(DIP) -55°cto+125° SE555CN 0404B 14-Pin Plastic Dual In-Line Package(DIP) -55℃t0+125°c 0405B 8-Pin Hermetic Cerdip -55°cto+125° SE555FE 14-Pin Ceramic Dual In-Line Package(CERDIP -55°cto+125° 0581B 14-Pin Ceramic Dual In-Line Package(CERDIP) -55°ct0+125° August 31, 1994 853003613721
Philips Semiconductors Linear Products Product specification Timer NE/SA/SE555/SE555C August 31, 1994 346 853-0036 13721 DESCRIPTION The 555 monolithic timing circuit is a highly stable controller capable of producing accurate time delays, or oscillation. In the time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. For a stable operation as an oscillator, the free running frequency and the duty cycle are both accurately controlled with two external resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the output structure can source or sink up to 200mA. FEATURES • Turn-off time less than 2µs • Max. operating frequency greater than 500kHz • Timing from microseconds to hours • Operates in both astable and monostable modes • High output current • Adjustable duty cycle • TTL compatible • Temperature stability of 0.005% per °C APPLICATIONS • Precision timing • Pulse generation • Sequential timing • Time delay generation • Pulse width modulation PIN CONFIGURATIONS 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 14 13 12 11 10 9 GND TRIGGER OUTPUT RESET GND NC TRIGGER OUTPUT NC RESET NC DISCHARGE THRESHOLD CONTROL VOLTAGE NC DISCHARGE NC THRESHOLD NC CONTROL VOLTAGE VCC VCC D, N, FE Packages TOP VIEW F Package ORDERING INFORMATION DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG # 8-Pin Plastic Small Outline (SO) Package 0 to +70°C NE555D 0174C 8-Pin Plastic Dual In-Line Package (DIP) 0 to +70°C NE555N 0404B 8-Pin Plastic Dual In-Line Package (DIP) -40°C to +85°C SA555N 0404B 8-Pin Plastic Small Outline (SO) Package -40°C to +85°C SA555D 0174C 8-Pin Hermetic Ceramic Dual In-Line Package (CERDIP) -55°C to +125°C SE555CFE 8-Pin Plastic Dual In-Line Package (DIP) -55°C to +125°C SE555CN 0404B 14-Pin Plastic Dual In-Line Package (DIP) -55°C to +125°C SE555N 0405B 8-Pin Hermetic Cerdip -55°C to +125°C SE555FE 14-Pin Ceramic Dual In-Line Package (CERDIP) 0 to +70°C NE555F 0581B 14-Pin Ceramic Dual In-Line Package (CERDIP) -55°C to +125°C SE555F 0581B 14-Pin Ceramic Dual In-Line Package (CERDIP) -55°C to +125°C SE555CF 0581B
Philips Semiconductors Linear Products Product specification Timer NE/SA/SE555/SE555C BLOCK DIAGRAM OLTAGE THRESH RESET OUTPUT OUTPU GND EQUIVALENT SCHEMATIC CONTROL VOLTAGE 此叶 TRIGGER NOTE: Pin numbers are for 8-Pin package August 31, 1994
Philips Semiconductors Linear Products Product specification Timer NE/SA/SE555/SE555C August 31, 1994 347 BLOCK DIAGRAM COMPARATOR COMPARATOR FLIP FLOP OUTPUT STAGE THRESHOLD VCC 6 7 3 1 4 2 5 8 R R R CONTROL VOLTAGE TRIGGER RESET DISCHARGE OUTPUT GND EQUIVALENT SCHEMATIC NOTE: Pin numbers are for 8-Pin package CONTROL VOLTAGE FM VCC R1 4.7K R2 330 R3 4.7 K R 4 1 K R 7 5 K R12 6.8K Q21 Q9 Q8 Q5 Q6 Q7 Q1 Q2 Q3 Q4 Q19 Q22 R13 3.9K OUTPUT Q23 C B R1 0 82. K R5 10 K Q10 Q11 Q12 Q13 Q20 R11 4.7K CB Q18 E R8 5K Q17 Q16 Q15 R6 100K R16 100 Q14 Q25 R9 5K R15 4.7K Q24 R14 220 THRESHOLD TRIGGER RESET DISCHARGE GND
Philips Semiconductors Linear Product Product specification Timer NE/SA/SE555/SE555C ABSOLUTE MAXIMUM RATINGS SYMBOL ARAMETER RATING UNIT Supply voltage NE555,SE555C,SA555 Operating ambient temperature range °C SA555 -40to+85 SE555. SE555C 55to+125 -65to+150 Lead soldering temperature(10sec max) +300 NOTES 1. The junction temperature must be kept below 125.C for the d package and below 150C for the FE, N and F packages At ambient tempera ures above 25.C, where this limit would be derated by the following factors FE package 150./w F package105°c/ August 31, 1994
Philips Semiconductors Linear Products Product specification Timer NE/SA/SE555/SE555C August 31, 1994 348 ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RATING UNIT Supply voltage VCC SE555 +18 V NE555, SE555C, SA555 +16 V PD Maximum allowable power dissipation1 600 mW TA Operating ambient temperature range NE555 0 to +70 °C SA555 -40 to +85 °C SE555, SE555C -55 to +125 °C TSTG Storage temperature range -65 to +150 °C TSOLD Lead soldering temperature (10sec max) +300 °C NOTES: 1. The junction temperature must be kept below 125°C for the D package and below 150°C for the FE, N and F packages. At ambient temperatures above 25°C, where this limit would be derated by the following factors: D package 160°C/W FE package 150°C/W N package 100°C/W F package 105°C/W
Philips Semiconductors Linear Products Product specification Timer NE/SA/SE555/SE555C DC AND AC ELECTRICAL CHARACTERISTICS TA=25.C, Vcc=+5v to +15 unless otherwise specified NE555/SE555C SYMBOL PARAMETER TEST CONDITIONS Mint typ T Maxt Min t Typ T MaxuNit Supply current (low 5V, RLS 6 mA Timing error(monostable) Ra=2kQ to 100kQ2 Initial accuracy C=0. 1uF % △tM/△T Drift with temperature 30 100 50150pmc 0.2 0.1 Timing error(astable RA, RB=lkE to 100kQ2 Initial accuracy % △ta/△T Drift with temperature Vcc=15v 500 500 ppm/oC Drift with supply voltage Control voltage level 9610010490100110 9410010688100112 Threshold voltage Vcc=5v 273.3340243.3342 Threshold curre 0.25 0.10.25 Trigger voltage 145167191.116722 0509 0520A Reset volta Vcc=15V,VTH=10.5V03 IESE Reset current VRESET=. 4V Reset current . mA Vcc=15v 010.15 01025 0.75 Output voltage(lot 2.0 2.2 2.0 2.5 SiNK=8mA 0.25 vvvvvv 00502 02503 IsoURCE=200mA 125 125 OH Output voltage(high) 130133 1275133 Vcc=5V IsouRCE=100mA 3.3 Turn-off time VRESET=VCC 0520 Rise time of output Fall time of output 100200100300ns DIscharge leakage current 20100 NOTES 1. Supply current when output high typically 1mA less. 2. Tested at Vcc=5V and Vcc=15V. the max value of RA+RB, for 15V operation, the max total R=10MQ2, and for 5v operation, the max total R=3. 4M cified with trigger input high. 5. Time measured from a positive going from 0 to 0. 8xVcc into the threshold to the drop from high to low of the output. Trigger is tied to threshold August 31, 1994
Philips Semiconductors Linear Products Product specification Timer NE/SA/SE555/SE555C August 31, 1994 349 DC AND AC ELECTRICAL CHARACTERISTICS TA = 25°C, VCC = +5V to +15 unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS SE555 NE555/SE555C SYMBOL PARAMETER TEST CONDITIONS UNIT Min Typ Max Min Typ Max UNIT VCC Supply voltage 4.5 18 4.5 16 V ICC Supply current (low VCC=5V, RL=∞ 3 5 3 6 mA state)1 VCC=15V, RL=∞ 10 12 10 15 mA Timing error (monostable) RA=2kΩ to 100kΩ tM Initial accuracy2 C=0.1µF 0.5 2.0 1.0 3.0 % ∆tM/∆T Drift with temperature 30 100 50 150 ppm/°C ∆tM/∆VS Drift with supply voltage 0.05 0.2 0.1 0.5 %/V Timing error (astable) RA, RB=1kΩ to 100kΩ tA Initial accuracy2 C=0.1µF 4 6 5 13 % ∆tA/∆T Drift with temperature VCC=15V 500 500 ppm/°C ∆tA/∆VS Drift with supply voltage 0.15 0.6 0.3 1 %/V VC Control voltage level VCC=15V 9.6 10.0 10.4 9.0 10.0 11.0 V VCC=5V 2.9 3.33 3.8 2.6 3.33 4.0 V VCC=15V 9.4 10.0 10.6 8.8 10.0 11.2 V VTH Threshold voltage VCC=5V 2.7 3.33 4.0 2.4 3.33 4.2 V ITH Threshold current3 0.1 0.25 0.1 0.25 µA VTRIG Trigger voltage VCC=15V 4.8 5.0 5.2 4.5 5.0 5.6 V VCC=5V 1.45 1.67 1.9 1.1 1.67 2.2 V ITRIG Trigger current VTRIG=0V 0.5 0.9 0.5 2.0 µA VRESET Reset voltage4 VCC=15V, VTH =10.5V 0.3 1.0 0.3 1.0 V IRESET Reset current VRESET=0.4V 0.1 0.4 0.1 0.4 mA Reset current VRESET=0V 0.4 1.0 0.4 1.5 mA VCC=15V ISINK=10mA 0.1 0.15 0.1 0.25 V ISINK=50mA 0.4 0.5 0.4 0.75 V VOL Output voltage (low) ISINK=100mA 2.0 2.2 2.0 2.5 V ISINK=200mA 2.5 2.5 V VCC=5V ISINK=8mA 0.1 0.25 0.3 0.4 V ISINK=5mA 0.05 0.2 0.25 0.35 V VCC=15V ISOURCE=200mA 12.5 12.5 V VOH Output voltage (high) ISOURCE=100mA 13.0 13.3 12.75 13.3 V VCC=5V ISOURCE=100mA 3.0 3.3 2.75 3.3 V tOFF Turn-off time5 VRESET=VCC 0.5 2.0 0.5 2.0 µs tR Rise time of output 100 200 100 300 ns tF Fall time of output 100 200 100 300 ns Discharge leakage current 20 100 20 100 nA NOTES: 1. Supply current when output high typically 1mA less. 2. Tested at VCC=5V and VCC=15V. 3. This will determine the max value of RA+RB, for 15V operation, the max total R=10MΩ, and for 5V operation, the max. total R=3.4MΩ. 4. Specified with trigger input high. 5. Time measured from a positive going input pulse from 0 to 0.8×VCC into the threshold to the drop from high to low of the output. Trigger is tied to threshold
Philips Semiconductors Linear Products Product specification Timer NE/SA/SE555/SE555C TYPICAL PERFORMANCE CHARACTERISTICS Minimum Pulse width Supply Current Delay Time Required for Triggering vs Supply Voltage vs Temperature 125°c Et-o>a +70°c 0. 4(AVcc) -50-250+25+50+75+100+125 LOWEST VOLTAGE LEVEL OF TRIGGER PULSE SUPPLY VOLTAGE- VOLTS Itage Low Output Voltage Low Output Voltage vS Output sink C Output Sink Current s Output sink Current +25°c 0.001 0.01 .020 1.02.0 5.0102050100 1.020 5.0102050100 Delay Time Propagation Delay vs Voltage vs Output Source Current vs Supply Voltage Level of Trigger Pulse 1.010 250 1.6 +70°c 2 ≤vcc≤15V 1.0205.01020 SOURCE- UPPLY VOLTAGE-V LOWEST VOLTAGE LEVEL OF TRIGGER PULSE-XVcc August 31, 1994
Philips Semiconductors Linear Products Product specification Timer NE/SA/SE555/SE555C August 31, 1994 350 TYPICAL PERFORMANCE CHARACTERISTICS Minimum Pulse Width Required for Triggering Supply Current vs Supply Voltage Low Output Voltage vs Output Sink Current Low Output Voltage vs Output Sink Current Low Output Voltage vs Output Sink Current Delay Time vs Temperature Delay Time vs Supply Voltage Propagation Delay vs Voltage Level of Trigger Pulse High Output Voltage Drop vs Output Source Current MINIMUM PULSE WIDTH (ns) LOWEST VOLTAGE LEVEL OF TRIGGER PULSE 150 125 100 75 50 25 0 0 0.1 0.2 0.3 0.4 (XVCC) -55oC 0oC +25oC +70oC +125oC 10.0 8.0 6.0 4.0 2.0 0 5.0 10.0 15.0 SUPPLY VOLTAGE – VOLTS SUPPLY CURRENT – mA 1.015 1.010 1.005 1.000 0.995 0.990 0.985 -50 -25 0 +25 +50 +75 +100 +125 NORMALIZED DELAY TIME TEMPERATURE – oC 10 1.0 0.1 0.001 1.0 2.0 5.0 10 20 50 100 10 1.0 0.1 0.01 1.0 2.0 5.0 10 20 50 100 10 1.0 0.1 0.01 1.0 2.0 5.0 10 20 50 100 1.0 2.0 5.0 10 20 50 100 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1.015 1.010 1.005 1.000 0.995 0.990 0.985 0 5 10 15 20 0 0.1 0.2 0.3 0.4 300 250 200 150 100 50 0 V – VOLTS OUT V – VOLTS OUT V – VOLTS OUT V – VOLTS OUT V CC NORMALIZED DELAY TIME PROPAGATION DELAY – ns I SINK – mA ISINK – mA ISINK – mA I SOURCE – mA SUPPLY VOLTAGE – V LOWEST VOLTAGE LEVEL OF TRIGGER PULSE – XVCC +125oC +25oC -55oC VCC = 5V VCC = 10V VCC = 15V -55oC +25oC +25oC -55oC +25oC +25oC +25oC +25oC -55oC -55oC 55oC +25oC +25oC –55oC +25oC +125oC 5V ≤ VCC ≤ 15V -55oC 0oC +25oC +70oC +25oC
Philips Semiconductors Linear Product Product specification Timer NE/SA/SE555/SE555C TYPICAL APPLICATIONS R FLOP OUTPUT OUTPUT Astable operation R VOLTAGE OUTPUT RESET Monostable Operation August 31, 1994
Philips Semiconductors Linear Products Product specification Timer NE/SA/SE555/SE555C August 31, 1994 351 TYPICAL APPLICATIONS OUTPUT FLIP FLOP COMP COMP f 1.49 (RA 2RB)C 555 OR 1/2 556 DISCHARGE CONTROL VOLTAGE THRESHOLD TRIGGER RESET OUTPUT R R C RB RA R 5 6 2 4 3 8 7 .01µF VCC OUTPUT FLIP FLOP COMP COMP 555 OR 1/2 556 DISCHARGE CONTROL VOLTAGE THRESHOLD TRIGGER RESET OUTPUT R R RA R 5 6 2 4 3 8 7 .01µF VCC ∆T = 1.1RC C 1 3VCC | ∆t | Astable Operation Monostable Operation
Philips Semiconductors Linear Products Product specification Timer NE/SA/SE555/SE555C TYPICAL APPLICATIONS OVOLTS TRIGGER PULSE AS ITCH GROUNDED NOTE: All resistor values are in o Figure 1. AC Coupling of the Trigger Pulse Trigger Pulse Width Requirements and Time Delays Another consideration is the"turn-off time". This is the measurement Due to the nature of the trigger circuitry, the timer will trigger on the of the amount of time required after the threshold reaches 2/3 Vc negative going edge of the input pulse. For the device to time out to turn the output low. To explain further, Q1 at the threshold input properly, it is necessary that the trigger voltage level be returned to tums on after reaching 2/3 Vcc, which then tums on Qs, which turns some voltage greater than one third of the supply before the time out on Qs. Current from Qs tums on Q16 which tums Q17 off. This period. This can be achieved by making either the trigger pulse allows current from Q1g to tum on @20 and Q24 to given an output sufficiently short or by AC coupling into the trigger By AC coupling low. These steps cause the 2us max delay as stated in the data the trigger, see Figure 1, a short negative going pulse is achieved when the trigger signal goes to ground. AC coupling is most frequently used in conjunction with a switch or a signal that goes to Also, a delay comparable to the turn-off time is the trigger release ground which initiates the timing cycle. Should the trigger be held time. When the trigger is low, Q10 is on and turms on Q11 which turn low, without AC coupling, for a longer duration than the timing cycle on Q15. @15 turns off Q16 and allows Q17 to turn on. This turms of g the output will remain in a high state for the duration of the low current to Q20 and Q24, which results in output high. When the igger signal, without regard to the threshold comparator state. This ased, Q10 and Q11 shut off, Q15 turns off, Q16 turns on is due to the predominance of Q15 on the base of Q16, controlling and the circuit then follows the same path and time delay explained the state of the bi-stable flip-flop. When the trigger signal the as "turn off time". This trigger release time is very important in eturns to a high level, the output will fall immediately. Thus, the designing the trigger pulse width so as not to interfere with the output signal will follow the trigger signal in this case output signal as explained previously August 31, 1994
Philips Semiconductors Linear Products Product specification Timer NE/SA/SE555/SE555C August 31, 1994 352 TYPICAL APPLICATIONS DURATION OF TRIGGER PULSE AS SEEN BY THE TIMER VCC VCC 10k 2 555 .001µF NOTE: All resistor values are in Ω Figure 1. AC Coupling of the Trigger Pulse 1 SWITCH GROUNDED AT THIS POINT OVOLTS 1/3 VCC VCC Trigger Pulse Width Requirements and Time Delays Due to the nature of the trigger circuitry, the timer will trigger on the negative going edge of the input pulse. For the device to time out properly, it is necessary that the trigger voltage level be returned to some voltage greater than one third of the supply before the time out period. This can be achieved by making either the trigger pulse sufficiently short or by AC coupling into the trigger. By AC coupling the trigger, see Figure 1, a short negative going pulse is achieved when the trigger signal goes to ground. AC coupling is most frequently used in conjunction with a switch or a signal that goes to ground which initiates the timing cycle. Should the trigger be held low, without AC coupling, for a longer duration than the timing cycle the output will remain in a high state for the duration of the low trigger signal, without regard to the threshold comparator state. This is due to the predominance of Q15 on the base of Q16, controlling the state of the bi-stable flip-flop. When the trigger signal then returns to a high level, the output will fall immediately. Thus, the output signal will follow the trigger signal in this case. Another consideration is the “turn-off time”. This is the measurement of the amount of time required after the threshold reaches 2/3 VCC to turn the output low. To explain further, Q1 at the threshold input turns on after reaching 2/3 VCC, which then turns on Q5, which turns on Q6. Current from Q6 turns on Q16 which turns Q17 off. This allows current from Q19 to turn on Q20 and Q24 to given an output low. These steps cause the 2µs max. delay as stated in the data sheet. Also, a delay comparable to the turn-off time is the trigger release time. When the trigger is low, Q10 is on and turns on Q11 which turns on Q15. Q15 turns off Q16 and allows Q17 to turn on. This turns off current to Q20 and Q24, which results in output high. When the trigger is released, Q10 and Q11 shut off, Q15 turns off, Q16 turns on and the circuit then follows the same path and time delay explained as “turn off time”. This trigger release time is very important in designing the trigger pulse width so as not to interfere with the output signal as explained previously