Interconnectivity Page 4 of 5 Application Notes: Using PDIUSBD12 in DMA Mode ISR. Any routines, that may want to be used to check DMA status, are not reliable because the DMA status during transfer may change at any time Below is an example of programming IN token DMa transfer, the dma dir and dma transfer_size have been set through Setup DMA Request: dma start(dma dir, MainDmaBuf, dma transfer size, 3) ma. bits. dma burst 3: dma. bits. dma enable =1 dma. bits. dma direction dma dir: dma. bits. auto reload =0; dma.bits. normal plus sof =0: ma. bits. endp 4 interrupt enable =0 dma. bits. endp 5 interrupt enable =0 D12 SetDMA(dma 4)Setup DMA Request firmware and test applet, this is done by IOCTL _WRITE_REGISTER, which is defined ample Setup DMA request is a vendor request that is sent through control pipe In PDIUSBD12 Microsoft Still Image USB Interface in Windows 98 DDK. Below is the device request description Offset Field SizeValue Comments 0 bmRequestType 0x4 Vendor request, device to host bRequest OOC Fixed value for IOCTL WRITE REGISTER WValue Offset,set to zero windex 2 0x0471 Fixed value of Setup DMA Request lEngth Data length of Setup DMA Request The details of requested DMA operation are sent in the data phase after the device request. The sample firmware and test applet use a proprietary definition which is shown below: Offset fi Comments The start address of requested DMA transfer 1 Address [15:8] [23:16 2345 size【7:0 The size of transfer Size [15: 8 Command Bit 7: 1 start DMA transfer Bit 0: 1'IN token:'0 oUT token 5)Host side Programming Considerations The USB device is not the only criteria, which decides the transfer rate. The performance of host de application plays a more important role in overall system performance because host always controls usB transactions The DMa transfer is a sequential operation that involves both control endpoint and Main endpoint Co-operation is impo because next step of operation is determined by the result of Philips Semiconductors-Asia Product Innovation Centre Visithttp://www.flexi usD. conInterconnectivity Page 4 of 5 Application Notes: Using PDIUSBD12 in DMA Mode ______________________________________________________________________________________________ Philips Semiconductors - Asia Product Innovation Centre Visit http://www.flexiusb.com ISR. Any routines, that may want to be used to check DMA status, are not reliable because the DMA status during transfer may change at any time. Below is an example of programming IN token DMA transfer, the dma_dir and dma_transfer_size have been set through Setup DMA Request: dma_start(dma_dir, MainDmaBuf, dma_transfer_size, 3); dma.bits.dma_burst = 3; dma.bits.dma_enable = 1; dma.bits.dma_direction = dma_dir; dma.bits.auto_reload = 0; dma.bits.normal_plus_sof = 0; dma.bits.endp_4_interrupt_enable = 0; dma.bits.endp_5_interrupt_enable = 0; D12_SetDMA(dma); 4) Setup DMA Request Setup DMA request is a vendor request that is sent through control pipe. In PDIUSBD12 sample firmware and test applet, this is done by IOCTL_WRITE_REGISTER, which is defined by Microsoft Still Image USB Interface in Windows 98 DDK. Below is the device request description: Offset Field Size Value Comments 0 bmRequestType 1 0x40 Vendor request, device to host 1 bRequest 1 0x0C Fixed value for IOCTL_WRITE_REGISTER 2 wValue 2 0 Offset, set to zero 4 wIndex 2 0x0471 Fixed value of Setup DMA Request 6 wLength 2 6 Data length of Setup DMA Request The details of requested DMA operation are sent in the data phase after the device request. The sample firmware and test applet use a proprietary definition which is shown below: Offset Field Comments 0 Address [7:0] The start address of requested DMA transfer. 1 Address [15:8] 2 Address [23:16] 3 Size [7:0] The size of transfer. 4 Size [15:8] 5 Command Bit 7: ‘1’ start DMA transfer Bit 0: ‘1’ IN token; ‘0’ OUT token 5) Host Side Programming Considerations The USB device is not the only criteria, which decides the transfer rate. The performance of host side application plays a more important role in overall system performance because host always controls USB transactions. The DMA transfer is a sequential operation that involves both control endpoint and Main endpoint. Co-operation is important because next step of operation is determined by the result of