Interconnectivity Page 3 of 5 Application Notes: Using PDIUSBD12 in DMA Mode Below is the flow chart of the firmware, which handles Setup DMA Request and EoT. Control Endp Save Setup DMA Request tate <-IDLE Program D figuration Register Request State IDLE? State < PENDING Program D12s ACK Device Request End of write 3)DMA Configuration Register The D12's DMA operation is controlled by its DMA Configuration Register, which is set by command Set DMA. Not all the bits inside the register are related to DMA operation. The bit 4 Interrupt Pin Mode, controls D12 sources of interrupt together with bit 7 of Clock Division Factor, SOF-ONLY Below is a summary of recommended register programming Bit DMA MO Non-DMA Mode 0&1 DMA Burst 1&1 Don't care DMA Enable DMA Direction 41 for IN token Don't care 0 for oUT token Auto reload Don't care Interrupt Pin Mode 0 6 Endpoint 4 Interrupt Enable Endpoint 5 Interrupt Enable By default, both of D12 and DMAC are not in auto-reload mode. We do not want the device's DMA"auto-restart because this is a protocol based operation, that is under host's control. At eot both of d12 and DMA controllers dma will be disabled. the firmware needs to re-enable them to restart DMA transfer upon receiving Setup DMA Request from the host Please also note that interrupt from endpoints 4 and 5 are disabled in DMA mode. Servicing interrupt on these endpoints is unnecessary and has a potential flaw during DMA transfer can be treated as highest "interrupt that happens between any CPU instructions, even inside Philips Semiconductors-Asia Product Innovation Centre Visithttp://www.flexi usD. conInterconnectivity Page 3 of 5 Application Notes: Using PDIUSBD12 in DMA Mode ______________________________________________________________________________________________ Philips Semiconductors - Asia Product Innovation Centre Visit http://www.flexiusb.com Below is the flow chart of the firmware, which handles Setup DMA Request and EOT. 3) DMA Configuration Register The D12’s DMA operation is controlled by its DMA Configuration Register, which is set by command Set DMA. Not all the bits inside the register are related to DMA operation. The bit 4, Interrupt Pin Mode, controls D12 sources of interrupt together with bit 7 of Clock Division Factor, SOF-ONLY. Below is a summary of recommended register programming: Bit Name DMA Mode Non-DMA Mode 0 & 1 DMA Burst ‘1’ & ‘1’ Don’t care 2 DMA Enable ‘1’ ‘0’ 3 DMA Direction ‘1’ for IN token; ‘0’ for OUT token Don’t care 4 Auto Reload ‘0’ Don’t care 5 Interrupt Pin Mode ‘0’ ‘0’ 6 Endpoint 4 Interrupt Enable ‘0’ ‘1’ 7 Endpoint 5 Interrupt Enable ‘0’ ‘1’ By default, both of D12 and DMAC are not in auto-reload mode. We do not want the device’s DMA “auto-restart” because this is a protocol based operation, that is under host’s control. At EOT, both of D12 and DMA controller’s DMA will be disabled. The firmware needs to re-enable them to restart DMA transfer upon receiving Setup DMA Request from the host. Please also note that interrupt from endpoints 4 and 5 are disabled in DMA mode. Servicing interrupt on these endpoints is unnecessary and has a potential flaw during DMA transfer. DMA can be treated as highest “interrupt” that happens between any CPU instructions, even inside Write Register Setup DMA Request? State = IDLE? Save Setup DMA Request Program DMAC Program D12's DMA Configuration Register State <- RUNNING ACK Device Request State <- PENDING End of Write Register Stall Control Endpoint Yes No Yes No EOT State = PENDING? Program DMAC Program D12's DMA Configuration Register State <- RUNNING ACK Device Request State <- IDLE End of EOT Yes No