课程安排 共54学时(18) 讲课,27学时 Verilog (5) Synthesis (3) Place &route (1) 实验,24学时 Verilog (5) Synthesis Place & route (1) 考试,3学时课程安排 • 共54学时 (18) • 讲课，27学时 – Verilog (5) – Synthesis (3) – Place &Route (1) • 实验，24学时 – Verilog (5) – Synthesis (2) – Place &Route (1) • 考试，3学时