方法2:使用 processi语句 library ieee use ieee std logic 1164. all use ieee std logic unsigned. all entity decoder is port(inp: in std logic vector(2 downto 0 outp: out std logic vector(7 downto O)) end decoder architecture rtl of decoder is begin process(inp) begin outp<=(others=>0) outp( conv integer(inp)-="1 end process end rtl9 方法2：使用process语句 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity decoder is port(inp : in std_logic_vector(2 downto 0); outp : out std_logic_vector(7 downto 0)); end decoder; architecture rtl of decoder is begin process(inp) begin outp<=(others=>’0’); outp(conv_integer(inp))<=‘1’; end process; end rtl;