方法1:使用逻辑左移运算符 library leee use ieee std logic 1164. all use ieee std logic unsigned. all entity decoder is port(inp: in std logic vector(2 downto 0 outp: out std logic vector(7 downto O)) end decoder architecture rtl of decoder is begin outp<=00000001 sll(conv integer(inp)) end rtl8 方法1：使用逻辑左移运算符 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity decoder is port(inp : in std_logic_vector(2 downto 0); outp : out std_logic_vector(7 downto 0)); end decoder; architecture rtl of decoder is begin outp<=“00000001” sll(conv_integer(inp)); end rtl;