TestBench Anatomy module My_tb; --TestBench module has no ports reg.… --Local signals and constants 土 wire......... TestBench Module Instantiating module; -Instantiations of DUT initial begin .........end --Input stimuli:clock Stimulus Generater Apply Inputs initial begin .........end --Input stimuli:reset initial begin .........end --Input stimuli:other signals initial begin ........end --Expected output Design Module Design Under Test always @posedge clock begin --Compare results end Response Monitor Observe Outputs always @posedge clock begin -Display results end endmodule 2021/1/13 ASIC Design,by Yan Bo 5ASIC Design, by Yan Bo TestBench Anatomy TestBench Module Design Module Stimulus Generater Apply Inputs Response Monitor Observe Outputs 2021/1/13 5 module My_tb; --TestBench module has no ports reg ……….; --Local signals and constants wire ……….; Instantiating module; -- Instantiations of DUT initial begin ……… end -- Input stimuli: clock initial begin ……… end -- Input stimuli: reset initial begin ……… end -- Input stimuli: other signals initial begin ……… end -- Expected output always @ ( posedge clock ) begin ……… -- Compare results end always @ ( posedge clock ) begin ……… -- Display results end endmodule Design Under Test