esTc 设计中 Putting it all together ENTITY cmpl sig Is ENTITY PORT( a, b, sel IN bit X, y, Z: OUT ARCHITECTURE END cmpl_sig ARCHITECTURE logic OF cmpl_ sig IS BEGIN X simple signal assignment x c(a AND NoT sel) OR(b AND se); sel conditional signal assignment y c a WHEN sel=O' ELSE b; selected signal assignment WITH sel SElECT i sel z<= a WHEN'O’ b When 0 WHEN OTHERS END logic. abe ∶sel CONFIGURATION cmpl_sig_ conf OF cmpl_sig IS FOR logic END FOR: END cmpl_sig_ conf;设计中心 Putting it all together