esTc 设计中 电子设计自动化技术 教师:李平教授(博导) Email: pliQuestc. edu.cn Te:83201794
设计中心 电子设计自动化技术 教师：李平教授（博导） Email: pli@uestc.edu.cn Tel: 83201794
esTc 设计中 电子设计自动化技术 第五章·续二
设计中心 电子设计自动化技术 第五章 · 续 二
esTc 设计中 Learning Vhdl must learn What is Combinatorial Logic What is Sequential Logic What is concurrent statement What is Process statement
设计中心 Learning VHDL must learn What is Combinatorial Logic What is Sequential Logic What is Concurrent Statement What is Process Statement
UesTC 设计中 g Combinatorial Logic if Outputs at a specified time are a function only of the inputs at that time e.g. decoders, multiplexers and adders LPM DIRECTION= LPM PIPELINE LPM REPRESENTATION ONE INPUT IS CONSTANT= LPM Output change nstantly when resul uTPUT result[3. 0] input change b30
设计中心 Combinatorial Logic • Combinatorial Logic if – Outputs at a specified time are a function only of the inputs at that time • e.g. decoders, multiplexers and adders Output change instantly when input change
esTc 设计中 Sequential Logic Sequential Logic if ,, 三,,, O utputs at a specified time are a function of the inputs at that time and at all preceding times All sequential circuits must include one or more registers e.g. State Machine, Counters, Shift Register and Controllers - LPM REPRESENTATION= LPM WIDTH= ONE INPUT IS CONSTANT= LPM AVALUE Outputs depends LPM ADD SUB on inputs and previous output a3.0] result[3. 0] Register is used to hold the previous value
设计中心 Sequential Logic • Sequential Logic if – Outputs at a specified time are a function of the inputs at that time and at all preceding times – All sequential circuits must include one or more registers • e.g. State Machine, Counters, Shift Register and Controllers Outputs depends on inputs and previous output Register is used to hold the previous value
esTc 设计中 Concurrent Statements There are several different kinds of Concurrent statements (1) Simple Signal Assignments (2) Conditional Signal Assignments (3) Selected Signal Assignments
设计中心 Concurrent Statements • There are several different kinds of Concurrent Statements – (1) Simple Signal Assignments – (2) Conditional Signal Assignments – (3) Selected Signal Assignments
esTc 设计中 Putting it all together ENTITY cmpl sig Is ENTITY PORT( a, b, sel IN bit X, y, Z: OUT ARCHITECTURE END cmpl_sig ARCHITECTURE logic OF cmpl_ sig IS BEGIN X simple signal assignment x c(a AND NoT sel) OR(b AND se); sel conditional signal assignment y c a WHEN sel=O' ELSE b; selected signal assignment WITH sel SElECT i sel z<= a WHEN'O’ b When 0 WHEN OTHERS END logic. abe ∶sel CONFIGURATION cmpl_sig_ conf OF cmpl_sig IS FOR logic END FOR: END cmpl_sig_ conf;
设计中心 Putting it all together
esTc 设计中 Process statement all the Process statement is executed in parallel Within the Process Statement, the coding s execute in sequential Process Statement is: OUTPUT depends on INPUT with Sensitivity List to control the event happen
设计中心 Process Statement • All the Process Statement is executed in parallel • Within the Process Statement, the coding is execute in sequential • Process Statement is : OUTPUT depends on INPUT with Sensitivity List to control the event happen
esTc 设计中 VHDL的一般格式及其语法规则 More Detail
设计中心 VHDL的一般格式及其语法规则 More Detail
esTc 设计中 延的语句 · WaIT clause · Attribute VHDL的顺序语句 Subprograms(function and procedure) · Block
设计中心 • 延时语句 • WAIT clause • Attribute • VHDL的顺序语句 • Subprograms (function and procedure) • Block
