电子设计自动化技术 第五章·VHDL 的主要描迷语勺
电子设计自动化技术 第五章 • VHDL 的主要描述语句
本节内容 Attribute VHDL的顺序语句 Wait LOOP ASSERT NEXT IF HEXIT CASE NULL
• Attribute • VHDL的顺序语句 本节内容 LOOP NEXT EXIT NULL Wait ASSERT IF CASE
属性( attributes) 属性:提供VHDL描述中的某些特殊信息 1.属性可描述的项目包括 types, subtypes, procedures, functions, signals, variables, constants entities, architectures, configurations packages, components f 2.一般格式:name' attribute_identifier VHDL具有一些预定义属性 X'event 当信号x上有事件发生时为真 last- value 一返回x上一时刻的值 yhigh 返回y取值范围的上界 x'stable(t 当x在过去的t时间内无事件发生 时为真
属性（attributes） • 属性：提供VHDL描述中的某些特殊信息 1. 属性可描述的项目包括types, subtypes, procedures, functions, signals, variables, constants, entities, architectures, configurations, packages, components等 2. 一般格式：name’attribute_identifier • VHDL具有一些预定义属性： x’event --当信号x上有事件发生时为真 x’last_value --返回x上一时刻的值 y’high --返回y取值范围的上界 x’stable(t) --当x在过去的t时间内无事件发生 时为真
属性( attributes) IF clkevent and clk1 THEN b<=a; End f ast value保证ck从0跳到1 IF clk' event and (clk1)and ( clklast value=“0)THEN b<= a End iF
IF clk’event and clk=‘1’ THEN b <= a ; End IF; IF clk’event and (clk=‘1’) and (clk’last_value = ‘0’) THEN b <= a ; End IF; • ‘last_value保证clk从’0’跳到’1’ 属性（attributes）
and is the signal name(any name) is a VHDL attribute, specifying that there needs to be a change in signal value is a change in value: from o' to 1, or from X to 1, etc means positive-edge triggered
• clk’event and clk=‘1’ – clk is the signal name (any name) – ‘event is a VHDL attribute, specifying that there needs to be a change in signal value – event is a change in value: from ‘0’ to ‘1’; or from ‘X’ to ‘1’, etc – clk=‘1’ means positive-edge triggered
a:IN STD_ LOGIC_VECTOR(7 DOWNTO O HGH=7 LOW- RIGHT-O LEFT-7 RANGE-7 DOWNTO O LENGTH-8
a : IN STD_LOGIC_VECTOR(7 DOWNTO 0) • ‘HIGH - 7 • ‘LOW - 0 • ‘RIGHT - 0 • ‘LEFT - 7 • ‘RANGE - 7 DOWNTO 0 • ‘LENGTH - 8
WAIT Statements WAT语句使进程挂起 WAIT [sensitivity_clause] [condition_clausel [timeout_clause] sensitivity_clause: wait on clockt condition clause: until boolean expression wait until clock=“1’3 timeout_clause: for time_expression wait for 150 ns;
WAIT Statements • WAIT语句使进程挂起 • WAIT [sensitivity_clause] [condition_clause] [timeout_clause] sensitivity_clause: on signal_name{, signal_name} wait on clock; condition_clause: until boolean_expression wait until clock = ‘1’; timeout_clause: for time_expression wait for 150 ns;
进程的(wait)等效描述 敏感信号( sensitive signals)与WAT ON process (a,b, cin) process begin begin sum < a XOR b XOR cin; sum <e a XoRb XOR cin; end process wait on a, b, cin; end process; 如果使用了 sensitivity_list,在 process中就不能使用WAT 语句 如果使用了WAT语句,在 process中就不能使用 sensitivity_list
进程的（wait）等效描述 • 敏感信号（sensitive signals）与WAIT ON process (a, b, cin) process begin begin sum <= a XOR b XOR cin; sum <= a XOR b XOR cin; end process; wait on a, b, cin; end process; NOTE: 如果使用了sensitivity_list，在process中就不能使用WAIT 语句 如果使用了WAIT语句，在process中就不能使用 sensitivity_list
IE-THENELSE VS WATIUNTIL Entity testl is IBRARY IEEE Entity testl is lport(clk, d: in bit SE IEEE std logic 1164. all port(clk, d: in bit q: out bit) ENTITY tdff IS q: out bit) nd test PORT(clk, d: in std_logic, end testl architecture testl b of testl is q: out std_logic); architecture testl b of testl gl END toff. begin process(clk, d) architecture behaviour OF tdff IS process(clk) BEGIN begin begin PROCESS if(clk="1'and clk'event)then if(clk='1")then q<=d; BEGIN <=d end if rait until clk=1 end if end proces d; end process lend test1 b END PROCESS end testl ENd behaviour 0aene题
IF-THEN-ELSE vs WATI UNTIL LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY tdff IS PORT(clk, d: in std_logic; q : out std_logic); END tdff; architecture behaviour OF tdff IS BEGIN PROCESS BEGIN wait until clk = '1'; q <= d; END PROCESS; END behaviour; Entity test1 is port (clk, d : in bit; q : out bit); end test1; architecture test1_b of test1 is begin process (clk) begin if (clk = ‘1’) then q <= d; end if; end process; end test1_b; Entity test1 is port (clk, d : in bit; q : out bit); end test1; architecture test1_b of test1 is begin process (clk,d) begin if (clk = ‘1’ and clk’event) then q <= d; end if; end process; end test1_b;
wait until与 wait for process egIn sum <= aXOR b XOR ci ob i iCl wait until a〓“’cm Clock end processy m process Nong ksa,两, 60 begin sum <e a XOR b XOR ci 0: wait for10ns;◆am end process sUm
wait until 与 wait for process begin sum <= a XOR b XOR cin; wait until a = ‘1’; end process; process begin sum <= a XOR b XOR cin; wait for 10 ns; end process;