系统结构描迷 COMPONENT语句 COMPONENT INSTANT语句
系统结构描述 COMPONENT语句 COMPONENT_INSTANT语句
COMP0NENT语旬 COMPONENT元件名 GENERIC说明】; PORT说明; END COMPONENT C0MP0NENT语句可以在 ARCHITECTURE PACKAGE ABLOCK 的说明部分中使用
COMPONENT语句 COMPONENT 元件名 【GENERIC 说明】； PORT 说明； END COMPONENT; COMPONENT语句可以在 ARCHITECTURE,PACKAGE及BLOCK 的说明部分中使用
Active HDL 6.1 (wdt wdt)-D: \My Designs\wdt\wdt\src\inv. vhd File Edit Search view Workspace Design Simulation Tools Window Help 匹器田哂琴厚分S的|B Design Browser 8晶A同t3 example library ieee: use ieee. std logic 1164.all uNsorted entity Inv 1s Fi Workspace 'wdt: 1 port (a: i td logic Add New Fi b: out sto工ogic) constant delay: time =4ns: 2 中、 /ipad.vhd end inv: t rtl awf architecture beh1 of inv 1s 忘bk02,awf 10 begin 3 自 half. vhd 11 b<=a after delay: 自Jhal2.vhd 12 end beh 5 圉Jinv,vhd 13 architecture beh2 of inv 1s 14 nv(beh2) begin 15 inv(beh1) b<=a after delay/2: 16 end beh2: 17 configuration slow of inv is slow 18 for heh 6 白自Jand2vhd 19 end for. and2〔t 20 end sloT 中圉 /mux. vhd 21 cn1 crural1nast口 Inv s mux(mix) 22 。pe2 e]ample 23 end for: +n wdt library 24 end正a彐t
D Active HDL 6.1(wdt, wdt)-D: \My_Designs\wdt\wdt\src\and2.vhd ile Edit Search View Workspace Design Simulation Tools window Help Design Browser S的pot3 Example library ieee: use leee·std1ogic1164·a11 uNsorted entity and2 is i Workspace'wdt': 1 port(a,b:in std logic; wdt c: out sto工ogic) Add new file end and2 中 Vwdtv architecture rt1。fana2i吕 中圉√ ipad. vhd begin i rtl. < a and b bko2, awF 10 end architecture rtl 3中圉 Half. vhd 11 aJhalf2vhd 12 中自√inv,vhd 13 5 6 中圉Jand2vhd 14 EA and2 (rtl) 15 16 中圉 Vmux. vhd 17 hfo wdt library 18
COMPONENT INStaNT语句 标号名:元件名 PORT MAP(信号,…) 该语句使得使用已有元件或模块成为 可能。该语句将元件或模块的端口信号 映射成为高层次电路中的信号
COMPONENT_INSTANT语句 标号名：元件名 PORT MAP（信号，•••） 该语句使得使用已有元件或模块成为 可能，该语句将元件或模块的端口信号 映射成为高层次电路中的信号
COMPONENT INStaNT语句 例:已有设计and2的端口说明如下 Port(a, b: in bit c: out bit) 元件调用 ul: and2 port map(x, y, g) u2: and2 port map (a=)x, b=>y, c=>q) 在输出信号没有连接的情况下。其对应 端口的描迷可以忽略
COMPONENT_INSTANT语句 例：已有设计and2的端口说明如下 Port（a,b:in bit; c:out bit); 元件调用 u1：and2 port map(x,y,q); u2: and2 port map(a=>x,b=>y,c=>q); 在输出信号没有连接的情况下，其对应 端口的描述可以忽略
Active HDL 6.1 (wdtwdt)-D: My Designs\wdt\wdt\src\mux. vhd File Edit Search View Workspace Design Simulation Tools Window Help 副器圃梦扁m?6|B均 Design Browser oi. port Example library ieee: use ieee. std logic 1164.all: Unsorted entity mux 1s Gii workspace'wdt': 1 port(in1, in2, sel:in std logic; wdt c: ut std工oqc) E Add New File end mux Eswtv architecture mix of nux 1s 自√ / ipad.vh component lnv i rtl awF port(a: in std工oqic bko2, awF b: out st工oqic) 自√ half. vhd end component: 4中Jha2vhd component and2 中圉Jinv,vhd port〔a,b: in std工oqic td工oqc) (beh) end component: Fast signal notsel: std logic. signal m1,m2: sta logic; begin 自√Jand2vhd u1: inv port map (a=>sel,b=>notsel): EAI and2 (rtl) 20 u2: and2 port map(sel, in1, m1); 自√ mux. vhd 21 u3: and2 port map (notsel, in2, m2): EAl mux(mix) c<=m1 or m2; end rmix. wdt library configuration example of mux is 。xmix for ul: inv use entity inv (beh1): 27 end for: 28 end for: end exarmp le
Active HDL 6.1 (wdt wdt)-D: My Designs\wdt\wdt\src\mux. vhd File Edit Search View Workspace Design Simulation Tools window Help 值回淼圃梦品Bm曾9B求虑 Design Browser example library ieee: 非 example:mu(mix) entity mux is ogic 1164.all: use leee. std l 非m:mw(beh1) Sline 11 port(in1, in2, sel:in sta logic; c: out std logic): 中非u2:and2(rt) end mux: 非u3:and2(rtl architecture mix。正muXi C line 22 component Inv std standard port(a: in std logiC. ieee std logic 1 164 10 b: out sta工oqic) end component: component and2 prt(a,b: in sto工ogic 14 c: out sta logic): 15 end component: Name value 16 signal notsel:std logic; sIdna1m1;m2:std工oqc b Unay begin u1: inv port map (a=>sel,b=>notsel): u2: and2 port map(sel, in1, m1): u3: and2 port map(notsel, in2, m2) C<=m1 or m2: a ml 24 configuration example of mux is 5 for m]x for u1: inv use entity inv (beh1): end for. 29 end ex
