functional HDE FSM BDE A options sImulation Active-HDL4. 2 optIons post-synthesis reports synthesis options simulation optIons ? 口 timing eports implementation options simulation Foundation
设计中心 Active-HDL4.2 FPGA Express Foundation
esTc 设计中 Training Introduction 个简单频率计的设计(带BCD计数器、LED 七段码显示控制) ·频率计的基本原理:将输入信号频率与基准时钟 频率进行比较 ·频率计在测量输入频率时,即测量状态下 START信号为1 该设计采用3三种描述模式:ⅥHDL行为代码模 式(HDE)、状态图模式(FSM)、框图模式(BDE) ·顶层框图将所有模块拼接起来
设计中心 Training Introduction • 一个简单频率计的设计（带BCD计数器、LED 七段码显示控制） • 频率计的基本原理：将输入信号频率与基准时钟 频率进行比较 • 频率计在测量输入频率时，即测量状态下 START信号为‘1’ • 该设计采用3三种描述模式：VHDL行为代码模 式(HDE)、状态图模式(FSM)、框图模式(BDE) • 顶层框图将所有模块拼接起来
UesTC 设计中 简单频率计框图 JHEX(O )LED(6-0)---DLED_A(6 EX2LED F INPUTD JHEX(0 )LED(6-0)---DLED B(6.0 PATTERNDF-PATTERN ICLK BCD A0 0/ BCD_A(3: 0) HEXLED BCD_B(3: 0) BCD_B(3: RESETDRESET GATE GATE BCD_C(: 0) BCD_ C3: 0) JHEXG O)LEDG D--DLED_C(6.0) END RESET STARTD-START END, RESET BCDD③:0) RESET BCD_D(: 0) HEX2LEI CONTROL CNT BCD JHEX(3-0)LED. --DLED_D(6.0) HEX2LED
设计中心 简单频率计框图
esTc 设计中 频率计主要模块 The following blocks are used in the design 一HEX2 LED -LED七段码显示转换模块(HDE) CNT BCD-4位十进制BCD计数器模块(BDE) (包含AND2和CNT4b俩子模块) CONTROL-频率计控制模块(FSM) Top frqm-顶层设计(BDE)
设计中心 频率计主要模块 • The following blocks are used in the design: – HEX2LED - LED七段码显示转换模块（HDE） – CNT_BCD - 4位十进制BCD计数器模块（BDE） (包含 AND2和 CNT_4b俩子模块) – CONTROL - 频率计控制模块（FSM） – Top_frqm - 顶层设计（BDE）
esTc 设计中 创建 Project( New Design) In the Type the design name field, enter FRQ METER New Design wizard Specify basic information about the new design Type the design name: FRO METER Select the location of the design folder: c: \my designs Browse The name of the default working library of the design FRO METER The name specified here will be used as the file name for wreaae- a5: the library files and as the logical name of the library. You &z can change the logical name later on Back E Next> Cancel
设计中心 创建Project (New Design) • In the Type the design name field, enter FRQ_METER
esTc 设计中 设计环境调整 Design Browser ·在 Design Browser点鼠标右键厂 Level selection 日 FRQ METER 选择 New Folder选项可以创建| File METER library 自己的文件夹 New G Add Files to Design 了 New Fold 新文件夹省却名为“ older1”、 Clear Implementation Data " Folder2”等,可以自行改名 多 Compile All Design Browser ·比如,我们可以创建名为 Top- Level selection FUNCTIONAL的文件夹,以便MT 归档我们接下来的设计 Add New File FUNCTIONAL f0 FRQ_METER library
设计中心 设计环境调整 • 在Design Browser 点鼠标右键 选择 New Folder 选项可以创建 自己的文件夹 • 新文件夹省却名为“Folder 1”、 “Folder 2”等, 可以自行改名 • 比如，我们可以创建名为 FUNCTIONAL的文件夹，以便 归档我们接下来的设计
esTc 设计中 设计内容 1.HEX2 LED- ED七段码显示转换模块 (HDE 2. CNT BCD-4位进制BCD计数器模(BDE) (包含AND2和CNT4b子模的) 3. Top frqm-顶层设计(BDE) 4. CONTROL-频率计控制模块(FSM)
设计中心 1. HEX2LED - LED七段码显示转换模块 （HDE） 2. CNT_BCD - 4位十进制BCD计数器模（BDE） (包含 AND2和 CNT_4b俩子模块) 3. Top_frqm - 顶层设计（BDE） 4. CONTROL - 频率计控制模块（FSM） 设计内容
New source file wizard- Ports To add a new port, click New To edit a port, select in on the list. Then you can change its name, direction and type To quickly change the index constraint of a port of a one-dimensional array type,use the Array Indexes box To remove a port, select it on the list, and then click Delete HE3可 HEX3: 0 Name: Array Indexes LED(6: 0 LED(6: 0] EDB6彐 Port direction lout out C buffe HEX2LED New Delete ype.. Back Cancel
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UesTC 设计中 1.2创建HEX2LED显示模块 ·HEX2 LED architecture:用 Language Assistant功能 调取 Language Assistant窗目: Tools| Language Assistant d Section below this comment is automatically maintained 选择 Synthesis and may be overwritten (entity (HEX2LED). Language Assistant 口区 Converter,用Use“厘 templates/ HEX2LED 01 IEEE HDL All--HEX-to-seven-segment decod A HXX. in STD LoGIC VEO 选项将代码放入 entity HEX2LED is D F/F with asynchronous Res LRD: out STD LOGIC VE D F/F with synchronous Reset architecture的 begin hEX: in STD 1 D Flip-Flop - segment encoding LED out sTD D Latch 与end之间 D Latch with Reset 8 end HEX2LED: Load register Note: The code is inserted where 1) End of automat2 Shift Register the cursor is located in your file Synchronous Counter[for INTE architecture heALeD Synchronous Counter(for STD with heX select Check this before you invoke the begin Tristate Buffer LED<="1111001"then" use command <enter your st+- Traini 0100100"then"0010 5end HEX2LED UM hex2led whd
设计中心 1.2 创建HEX2LED显示模块 • HEX2LED architecture: 用 Language Assistant功能 • 调取Language Assistant窗口：Tools | Language Assistant • 选择Synthesis templates / HEX2LED Converter，用Use 选项将代码放入 architecture 的begin 与 end之间. Note: The code is inserted where the cursor is located in your file. Check this before you invoke the use command
d section below this comment 2s automatically maintained and may be overwritten dentity (HEX2LED). Language Assistant 口区 國□《 012 library ieee use IEEE std logic 1 E Synthesis templates -HXX-to-sevex-segment decode Asynchronous Counter HEX. iN STD LOGIC VEC LEL out sTD LOGIC VEc 13 entity HEX2LED is D F/F with asynchronous Rese port D F/F with synchronous Reset D Flip-Flo segment encodin 5 hEX: in std] D Latch LeD: out sTD D Latch with Reset X2LED Converter 5 1 8 end HEX2LED; <-6 Load Register 19 Multiple: 0 1 End of automat2 Shift Register Synchronous Counter for INTE 22 architecture HEX2LED Synchronous Counter [for STD with heX select 3 begin . Tristate Buffer LED<="1111001"then" <<enter your st+ Training 0100100"then"00101 5 end HEX2LED eady NUM INS 7 iE hex2led whd
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