esTc 设计中 电子设计自动化技术 教师:李平教授(博导) Email: pliQuestc. edu.cn Te:83201794
设计中心 电子设计自动化技术 教师：李平教授（博导） Email: pli@uestc.edu.cn Tel: 83201794
esTc 设计中 电子设计自动化技术 第六章
设计中心 电子设计自动化技术 第六章
esTc 设计中 Designing Hierarchically
设计中心 Designing Hierarchically
esTc 设计中 Design Hierarchically-Multiple Design Files VHDL hierarchical design requires Component Declarations and Component Instantiations top. vhd entity-architecturetop" component“mid_a”, component“midb” mid a vhd mid b. vhd component“ bottom a entity-architecture"mid entity-architecture"mid b component“ bottom a component“ bottom b” bottom a vhd bottom b vhd entity-architecture"bottom_aLentity-architecture"bottom_b
设计中心 Design Hierarchically - Multiple Design Files • VHDL hierarchical design requires Component Declarations and Component Instantiations top.vhd entity-architecture “top” component “mid_a” ，component “mid_b” mid_a. vhd entity-architecture “mid_a” component “bottom_a” mid_b. vhd entity-architecture “mid_b” component “bottom_a” component “bottom_b” bottom_a. vhd entity-architecture “bottom_a” bottom_b. vhd entity-architecture “bottom_b
esTc 设计中 Component Declaration and Instantiation component Declaration -Used to declare the port types and the Data Types of the ports for a lower-level design. COMPONENT PORT( : sport type> ); END COMPONENT Component Instantiation -Used to map the ports of a lowerlevel design to that of the current-level design : PORT MAP(lower-level port name>=> ,.)
设计中心 Component Declaration and Instantiation • Component Declaration - Used to declare the Port types and the Data Types of the ports for a lower-level design. COMPONENT PORT ( : ; ……); END COMPONENT; • Component Instantiation - Used to map the ports of a lowerlevel design to that of the current-level design : PORT MAP( => , …);
esTc 设计中 Component Declaration and Instantiation Next-level of hierarchy design must have a Component Declaration for a lower-level design before it can be Instantiated ARCHITETURE structure view OF Full adder Is CoMPONENT half adder PORT(a, b: IN BIT; S, C: OUT BIT) END COMPONENT SIGNAL a b c BIT BEGIN u1: half adder PORT MAP(X,y, a, b) END structure_view
设计中心 Component Declaration and Instantiation • Next-level of hierarchy design must have a Component Declaration for a lower-level design before it can be Instantiated ARCHITETURE structure_view OF Full_adder IS COMPONENT half_adder PORT (a, b : IN BIT ;s ,c : OUT BIT); END COMPONENT; SIGNAL a,b,c:BIT; BEGIN u1: half_adder PORT MAP (x,y,a,b); …… END structure_view;
esTc 设计中 Benefits of Hierarchical Designing 1. In a design group, each designer can create separate functions(components)in separate design files. 2. These components can be shared by other designers or can be used for future projects 3. Therefore, designing hierarchically can make designs more modular and portable 4. Designing Hierarchically can also allow easier and faster alternative implementations
设计中心 Benefits of Hierarchical Designing 1. In a design group, each designer can create separate functions (components) in separate design files. 2. These components can be shared by other designers or can be used for future projects. 3. Therefore, designing hierarchically can make designs more modular and portable 4. Designing Hierarchically can also allow easier and faster alternative implementations
esTc 设计中 Example of hierarchical desian top. VHD middle vhd bottom inV VHD
设计中心 Example of hierarchical design bottom_inv.VHD middle.VHD top.VHD
esTc 设计中 ENTITY top心stop.HD END top ARCHITECTURE struc OF top Is COMPONENT middle GENER(n: POSITIVE万 PORT(input: IN BIT; output OUT BIT END COMPONENT. SIGNAL S1S2. BIT 标点符号 BEGIN U1: middle GENERIC MAP(n=>9) PORT MAP (input=>s1, output=>s2) END struc
设计中心 ENTITY top IS END top; ARCHITECTURE struc OF top IS COMPONENT middle GENERIC ( n : POSITIVE ); PORT(input : IN BIT; output : OUT BIT ); END COMPONENT; SIGNAL s1,s2 : BIT ; BEGIN U1: middle GENERIC MAP (n=>9) PORT MAP (input=>s1, output=>s2); END struc; top.VHD 标点符号
esTc 设计中 Example of hierarchical desian top. VHD middle vHD bottom inV VHD
设计中心 Example of hierarchical design bottom_inv.VHD middle.VHD top.VHD
