例: 四选一数据选择器 architecture abc of example Is signal sel: std logic vector(I downto 0) VHDL begin sek<=b &a: process(sel) 为什么 begin 顺序语句 还要 case sel Is others when“00”=>f=i0; when“01”→>f<=i1 when“10→>f<=i2 when“11”→f<=i3; ● when others=>nul end case; end process; end abc:V H D L 顺 序 语 句 例： 四选一数据选择器 architecture abc of example is signal sel:std_logic_vector(1 downto 0); begin sel<=b &a; process(sel) begin case sel is when “00” => f<=i0; when “01” => f<=i1; when “10” => f<=i2; when “11” => f<=i3; when others => null; end case; end process; end abc; 为什么 还要 others ?