组合运算模块的行为设计 library ieee; use ieee std_logic_arith.all; entity fir is port (x0, x1, X2, X3: in unsigned(15 downto 0); ho, h1, h2, h3: in unsigned (15 downto 0); y: out unsigned( 31 downto 0)) end fir architecture beh of fir is begin y<=x3*h0+x2*h1+x1*h2+x0*h3; end beh 综合结果:需要使用8194个LUT组合运算模块的行为设计 library ieee; use ieee.std_logic_arith.all; entity fir4 is port (x0,x1,x2,x3: in unsigned ( 15 downto 0 ); h0,h1,h2,h3: in unsigned ( 15 downto 0 ); y: out unsigned ( 31 downto 0 ) ); end fir4; architecture beh of fir4 is begin y<=x3*h0+x2*h1+x1*h2+x0*h3; end beh; 综合结果：需要使用8194个LUT ！