组合运算模块的 y: out unsigned downto 设计 architecture beh of fir is signal yo, yl,y2,y3: unsigned (31 downto O); begin y0<=X32h0y1<=X2h1y2<=x1h2y3<=x0 *h3 y<=yo(3l downto 16)+yl( 3l downto 16)+y2 (31 downto 16)+y3(31 downto 16) end beh 综合结果:需要使用7959个LUT 采用二进制符号数或无符号数,可以对运算过程进组合运算模块的行为设计 y: out unsigned ( 15 downto 0 ) ); ---- architecture beh of fir4 is signal y0,y1,y2,y3: unsigned (31 downto 0); begin y0<=x3*h0;y1<=x2*h1;y2<=x1*h2;y3<=x0 *h3; y<=y0(31 downto 16)+y1(31 downto 16)+y2(31 downto 16)+y3(31 downto 16); end beh; 综合结果：需要使用7959个LUT ！ 采用二进制符号数或无符号数，可以对运算过程进 行更准确的描述