Logical Register Transfers a rtl gives the meaning of the instructions a All start by fetching the instruction op rs rt rd shamt funct= MEM[ PC] op rs rt Imm16 MEM PC inst Register Transfers ADDU Rrd] <-R[rs]+ rrt PC <-PC +4 SUBU R[rd]<-R[rs-R[rt PC <-PC +4 ORi R[rt]<-R[rs] zero_ext(Imm16 PC <-PC +4 LOAD R[rt]<-MEMI R[rs]+ sign ext(Imm16)]: PC <-PC+4 STORE MEM[ R[s]+ sign ext(mm16)]<-Rrt]; PC <-PC+ 4 BEQ if( r[rs]== Rirt] then PC <-PC 4 +sign ext(Imm16)100 else pc <-PC +4 日209 Chapter4A7 CSE SJTU, 2017EI209 Chapter 4A.7 CSE, SJTU, 2017 Logical Register Transfers ❑ RTL gives the meaning of the instructions ❑ All start by fetching the instruction op | rs | rt | rd | shamt | funct = MEM[ PC ] op | rs | rt | Imm16 = MEM[ PC ] inst Register Transfers ADDU R[rd] <– R[rs] + R[rt]; PC <– PC + 4 SUBU R[rd] <– R[rs] – R[rt]; PC <– PC + 4 ORi R[rt] <– R[rs] | zero_ext(Imm16); PC <– PC + 4 LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4 STORE MEM[ R[rs] + sign_ext(Imm16) ] <– R[rt]; PC <– PC + 4 BEQ if ( R[rs] == R[rt] ) then PC <– PC + 4 +sign_ext(Imm16)] || 00 else PC <– PC + 4