Computer Organization Fa12017 Chapter 4A: The Processor, Part A [Adapted from Computer Organization and Design, 4th Edition, Patterson Hennessy, C 2012, MKI 日209 Chapter4A.1 CSE SJTU, 2017
EI209 Chapter 4A.1 CSE, SJTU, 2017 Computer Organization Fall 2017 Chapter 4A: The Processor, Part A [Adapted from Computer Organization and Design, 4th Edition, Patterson & Hennessy, © 2012, MK]
Review: MIPS(RISC)Design Principles a Simplicity favors regularity fixed size instructions small number of instruction formats opcode always the first 6 bits 口 Smaller is faster limited instruction set limited number of registers in register file limited number of addressing modes o Make the common case fast arithmetic operands from the register file(load-store machine allow instructions to contain immediate operands a Good design demands good compromises three instruction formats 日209 Chapter4A2 CSE SJTU, 2017
EI209 Chapter 4A.2 CSE, SJTU, 2017 Review: MIPS (RISC) Design Principles ❑ Simplicity favors regularity fixed size instructions small number of instruction formats opcode always the first 6 bits ❑ Smaller is faster limited instruction set limited number of registers in register file limited number of addressing modes ❑ Make the common case fast arithmetic operands from the register file (load-store machine) allow instructions to contain immediate operands ❑ Good design demands good compromises three instruction formats
The Processor: Datapath Control a Our implementation of the miPs is simplified memory-reference instructions: lw, sw arithmetic-logical instructions: add, sub, and, or, slt control flow instructions: beg, j a generic implementation use the program counter(PC)to supply Fetch the instruction address and fetch the =PC+4 instruction from memory(and update the PC) Exec Decode decode the instruction (and read registers) execute the instruction a All instructions(except j)use the ALU after reading the registers How? memory-reference? arithmetic? control flow? 日209 Chapter4A.3 CSE SJTU, 2017
EI209 Chapter 4A.3 CSE, SJTU, 2017 ❑ Our implementation of the MIPS is simplified memory-reference instructions: lw, sw arithmetic-logical instructions: add, sub, and, or, slt control flow instructions: beq, j ❑ Generic implementation use the program counter (PC) to supply the instruction address and fetch the instruction from memory (and update the PC) decode the instruction (and read registers) execute the instruction ❑ All instructions (except j) use the ALU after reading the registers How? memory-reference? arithmetic? control flow? The Processor: Datapath & Control Fetch PC = PC+4 Exec Decode
Aside: Clocking Methodologies a The clocking methodology defines when data in a state element is valid and stable relative to the clock State elements-a memory element such as a register Edge-triggered-all state changes occur on a clock edge a Typical execution read contents of state elements - send values through combinational logic -> write results to one or more state elements State Combinational State element logic element 2 clock one clock cycle O Assumes state elements are written on every clock cycle; if not, need explicit write control signal write occurs only when both the write control is asserted and the clock edge occurs 日209 Chapter4A.4 CSE SJTU, 2017
EI209 Chapter 4A.4 CSE, SJTU, 2017 Aside: Clocking Methodologies ❑ The clocking methodology defines when data in a state element is valid and stable relative to the clock State elements - a memory element such as a register Edge-triggered – all state changes occur on a clock edge ❑ Typical execution read contents of state elements -> send values through combinational logic -> write results to one or more state elements State element 1 State element 2 Combinational logic clock one clock cycle ❑ Assumes state elements are written on every clock cycle; if not, need explicit write control signal write occurs only when both the write control is asserted and the clock edge occurs
How to Design a Processor: step-by-step o 1. Analyze instruction set = datapath requirements the meaning of each instruction is given by the register transfers datapath must include storage element for ISa registers possibly more datapath must support each register transfer a 2. Select set of datapath components and establish clocking methodology a 3. Assemble datapath meeting the requirements a 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer 0 5 Assemble the control logic 日209 Chapter4A.5 CSE SJTU, 2017
EI209 Chapter 4A.5 CSE, SJTU, 2017 How to Design a Processor: step-by-step ❑ 1. Analyze instruction set => datapath requirements the meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers - possibly more datapath must support each register transfer ❑ 2. Select set of datapath components and establish clocking methodology ❑ 3. Assemble datapath meeting the requirements ❑ 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. ❑ 5. Assemble the control logic
The MiPs Instruction Formats o Al MIPS instructions are 32 bits long the three instruction formats 21 16 R-type rs shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 26 21 16 I-type rs immediate 6 bits 5 bits 5 bits 16 bits J-type 31 26 target address 6 bits 26 bits o The different fields are op: operation of the instruction rs,rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the"op" field address / immediate: address offset or immediate value target address: target address of the jump instruction 日209 Chapter4A.6 CSE SJTU, 2017
EI209 Chapter 4A.6 CSE, SJTU, 2017 The MIPS Instruction Formats ❑ All MIPS instructions are 32 bits long. The three instruction formats: R-type I-type J-type ❑ The different fields are: op: operation of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the “op” field address / immediate: address offset or immediate value target address: target address of the jump instruction op target address 31 26 0 6 bits 26 bits op rs rt rd shamt funct 31 26 21 16 11 6 0 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt immediate 31 26 21 16 0 6 bits 5 bits 5 bits 16 bits
Logical Register Transfers a rtl gives the meaning of the instructions a All start by fetching the instruction op rs rt rd shamt funct= MEM[ PC] op rs rt Imm16 MEM PC inst Register Transfers ADDU Rrd] <-R[rs]+ rrt PC <-PC +4 SUBU R[rd]<-R[rs-R[rt PC <-PC +4 ORi R[rt]<-R[rs] zero_ext(Imm16 PC <-PC +4 LOAD R[rt]<-MEMI R[rs]+ sign ext(Imm16)]: PC <-PC+4 STORE MEM[ R[s]+ sign ext(mm16)]<-Rrt]; PC <-PC+ 4 BEQ if( r[rs]== Rirt] then PC <-PC 4 +sign ext(Imm16)100 else pc <-PC +4 日209 Chapter4A7 CSE SJTU, 2017
EI209 Chapter 4A.7 CSE, SJTU, 2017 Logical Register Transfers ❑ RTL gives the meaning of the instructions ❑ All start by fetching the instruction op | rs | rt | rd | shamt | funct = MEM[ PC ] op | rs | rt | Imm16 = MEM[ PC ] inst Register Transfers ADDU R[rd] <– R[rs] + R[rt]; PC <– PC + 4 SUBU R[rd] <– R[rs] – R[rt]; PC <– PC + 4 ORi R[rt] <– R[rs] | zero_ext(Imm16); PC <– PC + 4 LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4 STORE MEM[ R[rs] + sign_ext(Imm16) ] <– R[rt]; PC <– PC + 4 BEQ if ( R[rs] == R[rt] ) then PC <– PC + 4 +sign_ext(Imm16)] || 00 else PC <– PC + 4
Step 1: Requirements of the Instruction Set 口 Memory instruction data a Registers(32×32) read Rs read rt Write rt or rd 口PC 口 Extender a Add and Sub register or extended immediate D Add 4 or extended immediate to pc 日209 Chapter4A.8 CSE SJTU, 2017
EI209 Chapter 4A.8 CSE, SJTU, 2017 Step 1: Requirements of the Instruction Set ❑ Memory instruction & data ❑ Registers (32 x 32) read RS read RT Write RT or RD ❑ PC ❑ Extender ❑ Add and Sub register or extended immediate ❑ Add 4 or extended immediate to PC
Step 1: Requirements of the Instruction Set 口 Memory(MEM) Instructions data (will use one for each: really caches) 口 Registers(R:32X32) Read rs Read rt Write rt orr 口PC a Extender (sign/zero extend) a Add/Sub/ORunit for operation on register(s)or extended immediate a Add 4(+ maybe extended immediate)to PC a Compare if registers equal? 日209 Chapter4A.9 CSE SJTU, 2017
EI209 Chapter 4A.9 CSE, SJTU, 2017 Step 1: Requirements of the Instruction Set ❑ Memory (MEM) Instructions & data (will use one for each: really caches) ❑ Registers (R: 32 x 32) Read rs Read rt Write rt or rd ❑ PC ❑ Extender (sign/zero extend) ❑ Add/Sub/OR unit for operation on register(s) or extended immediate ❑ Add 4 (+ maybe extended immediate) to PC ❑ Compare if registers equal?
Generic Steps of Datapath rd Loc①E rs ALU 0点 Imm 1. Instruction 2. Decode/ 3. EXecute 4. Memory 5. Register Fetch Register Write Read 日209 Chapter4A.10 CSE SJTU, 2017
EI209 Chapter 4A.10 CSE, SJTU, 2017 Generic Steps of Datapath instruction memory +4 rt rs rd registers ALU Data memory imm 1. Instruction Fetch 2. Decode/ Register Read 3. Execute 4. Memory5. Register Write PC mux
