disp_flag<='0'; end if; end if; end process process(clk) begin if(clk'event and clk='1')then if(disp_flag='1')then case din h is when "0000"=>adh<="0111111";--display 0 。年。中。3 when"1111"=>adh<="1110001": --display f when others=>adh<=adh: --no change end case; case din_1 is when000"=>ad1<="0111111": --display 0 when"1111"=>ad1<="1110001": --display f when others=>adl<=adl; --no change end case; end if; end if; end process; process(clk) --display process begin if(clk'event and clk='1')then dcount<=dcount+l; sa<=dcount (0); sb<=dcount(1); sc<=dcount(2); case dcount is when"111"-=>display<="1110111": --display A when"000"=>display<="1011110": --display d when"001"=>display<="0111001" --display C when"010"=>display<←"1000000"： --display when"011"=>display<="1000000": --display when "100"=>display<=adh; when "101"=>display<=adl; when"110"=>display<="1110100": --display h when others=>display<=0000000": end case; end if; end process; process(clk) --In this process,a,b,c,d,e,f,g and dot will output begin if(clk'event and clk='1')then a<=display(0); g<=display(6); end if; end process end behave; 七、实验报告要求 对于外部模拟信号Vtest范围超出0~5V的情况下，应如何修改设计和显示模块？ 请学生思考：为什么引入CLK信号？用与不用CLK信号对显示可能产生什么影响？disp_flag<='0'; end if; end if; end process; process(clk) begin if(clk'event and clk='1') then if(disp_flag='1') then case din_h is when "0000"=>adh<="0111111"; --display 0 …… when "1111"=>adh<="1110001"; --display f when others=>adh<=adh; --no change end case; case din_l is when "0000"=>adl<="0111111"; --display 0 …… when "1111"=>adl<="1110001"; --display f when others=>adl<=adl; --no change end case; end if; end if; end process; process(clk) --display process begin if(clk'event and clk='1') then dcount<=dcount+1; sa<=dcount(0); sb<=dcount(1); sc<=dcount(2); case dcount is when "111"=>display<="1110111"; --display A when "000"=>display<="1011110"; --display d when "001"=>display<="0111001"; --display C when "010"=>display<="1000000"; --display - when "011"=>display<="1000000"; --display - when "100"=>display<=adh; when "101"=>display<=adl; when "110"=>display<="1110100"; --display h when others=>display<="0000000"; end case; end if; end process; process(clk) --In this process, a,b,c,d,e,f,g and dot will output begin if(clk'event and clk='1') then a<=display(0); …… g<=display(6); end if; end process; end behave; 七、 实验报告要求 对于外部模拟信号 Vtest 范围超出 0～5V 的情况下，应如何修改设计和显示模块？ 请学生思考：为什么引入 CLK 信号？用与不用 CLK 信号对显示可能产生什么影响？