康林科技 【例93】 工工 BRARY工EEE; USE IEEE STD LOGIC 1164.ALL; UsE工西. STD LOG工 C UNSIGNED.ATL ENTITY alu工s PORT( b: IN STD LOGIC VECTOR (7 DOWNTo 0)i opcode IN STD LOGIC VECTOR (1 DOWNTo 0)i result: OUT STD LOGIC VECTOR (7 DOWNTO 0))i END alui ARCH工 TECTURE behave of a1u工s CONSTANT plu STD LOGIC VECTOR (1 DOWNTo 0): =boo; CONSTANT minus STD LOGIC VECTOR (1 DOWNTO 0):= b0l" CONSTANT equa工 :SD工OG工 VECTOR(1DoMNⅣo0):b"10"; CONSTANT not equal: STD LOGIC VECTOR (1 DOWNTo 0):=b1l BEG工N PROCESS (opcode, a,b) BEG工N CASE opcode工s WHen plus result < a+ bi a、b相加 WHEN minus = result <= a -bi a、b相减 WHEn equal = a、b相等 接下页KX 康芯科技 【例9-3】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY alu IS PORT( a, b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); opcode: IN STD_LOGIC_VECTOR (1 DOWNTO 0); result: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END alu; ARCHITECTURE behave OF alu IS CONSTANT plus : STD_LOGIC_VECTOR (1 DOWNTO 0) := b"00"; CONSTANT minus : STD_LOGIC_VECTOR (1 DOWNTO 0) := b"01"; CONSTANT equal : STD_LOGIC_VECTOR (1 DOWNTO 0) := b"10"; CONSTANT not_equal: STD_LOGIC_VECTOR (1 DOWNTO 0) := b"11"; BEGIN PROCESS (opcode,a,b) BEGIN CASE opcode IS WHEN plus => result <= a + b; -- a、b相加 WHEN minus => result <= a - b; -- a、b相减 WHEN equal => -- a、b相等 接下页