K述列 91顺序语句 91.1赋值语句 之之信号赋值语句 变量赋值语句 贼值目标 赋值符号 赋值源 912IF语句
KX 康芯科技 9.1 顺序语句 9.1.1 赋值语句 9.1.2 IF 语句 信号赋值语句 变量赋值语句 赋值目标 赋值符号 赋值源
K述列 91顺序语句 CASE语句的结构如下: 913CASE语句 CASE表达式Is When选择值=>顺序语句; When选择值=>顺序语句; END CASE >选择值可以有四种不同的表达方式 多条件选择值的一般表达式为:单个普通数值,如6 数值选择范围,如(2To4),表示取值为 选择值[选择值] 2、34。 并列数值,如35,表示取值为3或者5 混合方式,以上三种方式的混合
KX 康芯科技 9.1 顺序语句 9.1.3 CASE语句 CASE语句的结构如下: CASE 表达式 IS When 选择值 => 顺序语句; When 选择值 => 顺序语句; ... END CASE ; 多条件选择值的一般表达式为: 选择值 [ |选择值 ] 选择值可以有四种不同的表达方式: 单个普通数值,如6。 数值选择范围,如(2 TO 4),表示取值为 2、3或4。 并列数值,如35,表示取值为3或者5。 混合方式,以上三种方式的混合
【例9-1】 工工 BRARY工; USE IEEE STD LOGIC 1164.ALL: ENTITY mux41 IS ORT(s4, s3, s2, s1: IN STD LOGICi z4, z3, z2, Z1: OUT STD LOGIC) END mux41 ARcH工 TECTURE ad七 1v OF mUX41工s SIGNAL sel: INTEGER RANGE 0 To 15; BEGIN PROCESs (sel s4, s3, s2, s1) BEGIN se1<=0; 输入初始值 IF (sl =1 THEN sel < sel+l i ElSIF (s2 =1)THEN sel < sel+2 ElSIF ( s3 =1 THEN sel < sel+4 i ElSIF (s4=l')THEN sel < sel+8 i ELSE NULL 注意,这里使用了空操作语句 END工F; z1<=·0;z2<=10";z3<="0';z4<="0"; 输入初始值 CASE sel IS WHeN o z1<=11!; 当se]=0时选中 接下页
KX 康芯科技 【例9-1】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux41 IS PORT (s4,s3, s2,s1 : IN STD_LOGIC; z4,z3, z2,z1 : OUT STD_LOGIC); END mux41; ARCHITECTURE activ OF mux41 IS SIGNAL sel : INTEGER RANGE 0 TO 15; BEGIN PROCESS (sel ,s4,s3,s2,s1 ) BEGIN sel z1<='1' ; -- 当sel=0时选中 接下页
康芯科技 MHEN13=>z2z3z4 out1<=I0 END CASE CASE value Is WHEN0To10=。ut1<=11!; 选择值中5~10的值有重叠 WHEN 5 To 15 = outl<=0i END CASE;
KX 康芯科技 WHEN 13 => z2 z3 z4 out1 out1 out1 out1<= '0'; END CASE;
康林科技 【例93】 工工 BRARY工EEE; USE IEEE STD LOGIC 1164.ALL; UsE工西. STD LOG工 C UNSIGNED.ATL ENTITY alu工s PORT( b: IN STD LOGIC VECTOR (7 DOWNTo 0)i opcode IN STD LOGIC VECTOR (1 DOWNTo 0)i result: OUT STD LOGIC VECTOR (7 DOWNTO 0))i END alui ARCH工 TECTURE behave of a1u工s CONSTANT plu STD LOGIC VECTOR (1 DOWNTo 0): =boo; CONSTANT minus STD LOGIC VECTOR (1 DOWNTO 0):= b0l" CONSTANT equa工 :SD工OG工 VECTOR(1DoMNⅣo0):b"10"; CONSTANT not equal: STD LOGIC VECTOR (1 DOWNTo 0):=b1l BEG工N PROCESS (opcode, a,b) BEG工N CASE opcode工s WHen plus result < a+ bi a、b相加 WHEN minus = result <= a -bi a、b相减 WHEn equal = a、b相等 接下页
KX 康芯科技 【例9-3】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY alu IS PORT( a, b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); opcode: IN STD_LOGIC_VECTOR (1 DOWNTO 0); result: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END alu; ARCHITECTURE behave OF alu IS CONSTANT plus : STD_LOGIC_VECTOR (1 DOWNTO 0) := b"00"; CONSTANT minus : STD_LOGIC_VECTOR (1 DOWNTO 0) := b"01"; CONSTANT equal : STD_LOGIC_VECTOR (1 DOWNTO 0) := b"10"; CONSTANT not_equal: STD_LOGIC_VECTOR (1 DOWNTO 0) := b"11"; BEGIN PROCESS (opcode,a,b) BEGIN CASE opcode IS WHEN plus => result result -- a、b相等 接下页
K述列 接上页 IF(a= b)THEn result <=xol EL SE result < x O01 END工F; WHEN not equal = a、b不相等 IF (a/= b)THEN result<=x01 ELSE result <= xooi END工F; END CASE END PROCESS ENd behave;
KX 康芯科技 IF (a = b) THEN result -- a、b不相等 IF (a /= b) THEN result <= x"01"; ELSE result <= x"00"; END IF; END CASE; END PROCESS; END behave; 接上页
K述列 9.14LOOP语句 (1)单个LOOP语句,其语法格式如下: [工oOP标号:]工ooP 顺序语句 END LOOPILOOP标号; 感感 用法示例如下: 工2:1ooP a+1; Ex工2 WHEN>10 当a大于10时跳出循环 END LOOP L2; (2) FOR LOOP语句,语法格式如下: [LoOP标号:]FOR循环变量,IN循环次数范围Loop 顺序语句 END LOOP LOOP标号];
KX 康芯科技 9.1.4 LOOP语句 (1)单个LOOP语句,其语法格式如下: [ LOOP标号:] LOOP 顺序语句 END LOOP [ LOOP标号]; (2)FOR_LOOP语句,语法格式如下: [LOOP标号:] FOR 循环变量,IN 循环次数范围 LOOP 顺序语句 END LOOP [LOOP标号]; 用法示例如下: ... L2 : LOOP a := a+1; EXIT L2 WHEN a >10 ; -- 当a大于10时跳出循环 END LOOP L2;
【例94】 工工 BRARY工EEE; USE IEEE STD LOGIC 1164.ALL: ENTITY p check工S PoRT a: IN STD LOGIC VECTOR (7 DOWNTo 0) Y: OUT STD LOGIC )i END p check; ARCHITECTURE opt of p check IS SIGNAL tmp: STD LOG工c BEG工N PROCESS (a) BEG工N tmp <=10 FOR n IN 0 TO 7 LOOP tmp < tmp XOR a(n)i END工ooP y < tmp; END PROCESS END opt
KX 康芯科技 【例9-4】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY p_check IS PORT ( a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); y : OUT STD_LOGIC ); END p_check; ARCHITECTURE opt OF p_check IS SIGNAL tmp :STD_LOGIC ; BEGIN PROCESS(a) BEGIN tmp <='0'; FOR n IN 0 TO 7 LOOP tmp <= tmp XOR a(n); END LOOP ; y <= tmp; END PROCESS; END opt;
K述列 多 【例95】 SIGNAL a, b, c: STD LOGIC VECTOR (1 To 3) FoR n IN 1 To 3 LOOP a(n)<=b(n) AND c(n)i END LOOP: 此段程序等效于顺序执行以下三个信号赋值操作: a(1)<=b(1)ANDc(1); a(2)<=b(2)ANDc(2) a(3)<=b(3)ANDc(3);
KX 康芯科技 【例9-5】 SIGNAL a, b, c : STD_LOGIC_VECTOR (1 TO 3); ... FOR n IN 1 To 3 LOOP a(n) <= b(n) AND c(n); END LOOP; 此段程序等效于顺序执行以下三个信号赋值操作: a(1)<=b(1) AND c(1); a(2)<=b(2) AND c(2); a(3)<=b(3) AND c(3);