ALU指令完成时间：Id与ALU Time (in clock cycles) CC1 CC2 CC3 CC4 CC5 CC6 CC 1 CC2 CC3 Program execution Load Ifetch Reg Exec Mem Wr order (in instructions) R-type Ifetch Reg Exec Wr w$10,20($1) RF写端口结构冲突 sub$11,$2,$3 add$12,s3,$4 w$13,24($1) add$14,s5,$6 M ALU 1010 ALU指令完成时间：ld与ALU RF写端口结构冲突