ARCHITECTURE test bench Of test and2 gate IS COMPONENT and2 GENERIC(RS, Fl: time) PORT (a, b: IN my qsim 12state OUT my gsim 12state) END COMPONENT FOR al: and2 USE ENTITY and2 gate( behav GENERIC MAP(RS, FD PORT MAP (a, b, c) SIGNAL X, y,z: my qsim 12state BEGIN al. and2 GENERIC MAP (7 ns, 10 ns) PORT MAP(X, y, Z); ENd test benchARCHITECTURE test_bench OF test_and2_gate IS COMPONENT and2 GENERIC (Rs, Fl : time); PORT (a, b : IN my_qsim_12state; c : OUT my_qsim_12state); END COMPONENT; FOR a1 : and2 USE ENTITY and2_gate(behav) GENERIC MAP (Rs, Fl) PORT MAP (a, b, c); SIGNAL x, y, z : my_qsim_12state; BEGIN a1 : and2 GENERIC MAP (7 ns, 10 ns); PORT MAP (x, y, z); END test_bench;