Contents xi 4.3.2 SEQ Hardware Structure 396g).) 4.3.3 SEQ Timing 400 2子母 4.3.4 SEQ Stage Implementations 404 4.4 General Principles of Pipelining 4121,. 4.4.1 Computational Pipelines 412 4.4.2 A Detailed Look at Pipeline Operation 414 4.4.3 Limitations of Pipelining 416 4.4.4 rPipelining aSystem with Feedback 419 17 4.5 Pipelined Y86-64 Implementations.421 4.5.1 SEQ+:Rearranging the Computation Stages,421 4.5.2 Inserting.Pipeline Registers 422 4.5.3 Rearranging and Relabeling Signals 426 4.5.4 Next PC Prediction 427 4.5.5 Pipeline Hazards 429 4.5.6 Exception Handling 444 4.5.7 PIPE Stage Implementations 447 4.5.8 Pipeline Control Logic 455 4.5.9-Performance Analysis _464 4,5.10 Unfinished Business 468 4.6 Summary 470 4.6.1 Y86-64 Simulators 472 Bibliographic Notes 473 Homework Problems 473 Solutions to Practice Problems 480 5 Optimizing Program Performance:495 5.1 Capabilities and Limitations of Optimizing Compilers 498 5.2 Expressing Program Performance.502 53 Program Example 504 5.4 Eliminating Loop'Inefficiencies 508 5.5 Reducing Procedure Calls 512 .d 5.6 Eliminating Unneeded Memory References,514 5.7 Understanding Modern Processors 517. 5.7.1 Overall Operation 518 5.7.2 Functional Unit Performance 523 5.7.3 An Abstract Model of Processor Operation 525 5.8 Loop Unrolling 53br 59 Enhancing Parallelism 536 5.9.1 Multiple.Accumulators 536 5.9.2 Reassociation Transformation 5414.3.2 SEQ Hardware Structure 396G0 . ,. '· ' • 1., • ·' 4.3.3 SEQ Timing 400 ·¥. " ,. '! n•J '"" 4.3.4 SEQ Stage Jmplementations 404 11"' ., ' 4.4 General Principles of Pipelining 412 , l" 4.4.1 Coi;nputat~onal Pipelines 412· '(It .t/ 4.4.2 A Detailed Look at Pipeline Operation,. il14l 4.4.3 Limit,atiqns of Pipelining 416 4.4.4 <•,l?ipelihingc.a'System with Feedback· 419 1 , :. 4.5 Pipelined Y86'64 Impleinentations• '421·tJ .·11< 4.5.l SEQ+: Rearranging the Computation Stagesu-.421 4.5.2 Insefting.Pipeline Registers 422 , .fi" 4.5.3 Rearranging and Relabeling Signals 426 4.5.4 Next PC Prediction 427 • > 4.5.5 Pipeline Hazards 429 4.5.6 Exception Handling 444 _, 4.5.7 PIPE Stage Implementations 447 4.5.8 Pipeline Control Logic 455 4.5.9 - Performance Analysis -464. 4,5.10 Unfinisped Business 468 4.6 Summary 470 5 4.6.1 Y86-64 Simulators 472 Bibliographic Notes 473 Homework Problems 473 Solutions to Practice Problems 480 . . ,, Optimizing Program'P'erforniqnc~; 495 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Capabilities and Limitations· of Optimizing Compilers 1198 Expressing Program Performance. ·502 Program Example 504 Eliminating Loop•I:gefficiencies 508 .J• Reducing Procedure Calls 51'.Z.< '" " Eliminating Unneeded Memory Referencesu514 ... Understanding Modern Processors ·517,. 5.7.l Overall Operation 518 5.7.2 Functional Unit Performance 523 5.7.3 An Abstract Model of Processor Operation 525 5.8 Loop Unrolling 53.hr" "' 5.9 Enhanqing Parallelism 536 5.9.l Multiple.Accumulators 536 5.9.2 Reassociation Transformation 541 ~Contents xi