Share resources (Cont.) module test(rst,clk,updn,q); +1 clk rst inputrst,clk,updn; output [7:0]q; reg[7:0]q; always@(posedge clk or negedge rst) q begin Registers if (!rst)q<=0; else if (updn)q<=q+1; else q<=q-1; end endmodule module test(rst,clk,updn,q); inputrst,clk,updn; clk rst output [7:0]q; reg [7:0]q; integer dir; always@(posedge clk or negedge rst) Registers q if (Irst) q<=0; else q<=q+dir; always @(updn) if (updn)dir=1; else dir =-1; endmodule 2021/1/13 ASIC Design,by Yan Bo 15ASIC Design, by Yan Bo Share resources （Cont.） 2021/1/13 15 module test(rst, clk, updn, q); input rst, clk, updn; output [7:0] q; reg [7:0] q; always@(posedge clk or negedge rst) begin if (!rst) q<=0; else if (updn) q<=q+1; else q<=q-1; end endmodule + Registers +1 -1 q clk rst + module test(rst, clk, updn, q); input rst, clk, updn; output [7:0] q; reg [7:0] q; integer dir; always@(posedge clk or negedge rst) if (!rst) q<=0; else q<=q+dir; always @ (updn) if (updn) dir = 1; else dir = -1; endmodule + Registers q clk rst +1 -1