VHDL与 Verilog HDL的对比 2.外部端口描述 entity mux is port(: in std logic vector(1 downto 0) a, b, c, d: in std logic vector (7 downto 0 y: out std logic vector (7 downto O)); end muxi module kmux4 1(s, a, b, c,d,y); input[1: 0]s; input [ 7: 0] a, b, c, d output7: 0ly2．外部端口描述 entity mux4 is port (s: in std_logic_vector(1 downto 0); a,b,c,d: in std_logic_vector(7 downto 0); y: out std_logic_vector( 7 downto 0)); end mux4; module kmux4_1(s,a,b,c,d,y); input[1:0] s; input [7:0] a,b,c,d; output[7:0] y; VHDL 与 Verilog HDL 的对比