寻址存储器设计:16X8位RAM library ieee use ieee std logic 1164. all use ieeestd logic unsigned. all entity kram is port (clk, wr, cs: in std logic d: inout std logic vector(7 downto 0) adr: in std logic vector (3 downto O) end kram:library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity kram is port ( clk,wr,cs: in std_logic; d: inout std_logic_vector(7 downto 0); adr: in std_logic_vector(3 downto 0)); end kram; 寻址存储器设计： 16x8位RAM