寻址存储器设计:16X8位RAM architecture beh of kram is subtype word is std logic vector (7 downto 0) type memory is array(0 to 15) of word; signal adr in: integer 0 to 15; SIgnal sram: memory begin adr in<=conv integer (adr); 将地址转换为数组下标 process(clk) beginarchitecture beh of kram is subtype word is std_logic_vector(7 downto 0); type memory is array (0 to 15) of word; signal adr_in:integer range 0 to 15; signal sram:memory; begin adr_in<=conv_integer (adr); --将地址转换为数组下标 process(clk) begin 寻址存储器设计： 16x8位RAM