834 IEEE Transactions on Consumer Electronics,Vol.48,No.4,NOVEMBER 2002 A HIGH-SPEED,PROGRAMMABLE,CSD COEFFICIENT FIR FILTER Zhangwen Tang,Jie Zhang and Hao Min ASIC System State-Key Laboratory,Fudan University,Shanghai 200433,P.R.China Xin回回回……。 Abstrac-A new high-speed,programmable FIR filter is presented,which is a multiplierless filter with CSD encoding coefficients.In this paper,we propose a new programmable X-0X-0)X-i--h0 CSD encoding structure to make CSD coefficients programmable.Compared with the conventional FIR structure with Booth multipliers,this coding structure improves the speed of filter and decreases the area.In the end of this paper,we design a 10-blts,18-taps video luminance filter with the presented filter structure.The completed filter core occupies 6.86.8 mm2 of silicon area in 0.6um 2P2M Yout CMOS technology,and its maximum work frequency is 100MHz. Fig.1.Structure of traditional FIR filter Index terms-Finite Impulse Response filter,Application cannot accommodate such high sample rates without an Specific Integrated Circuit,Canonic Signed-digit Encode, excessive amount of parallel processing.And for dedicated Booth Multiplier.Wallace Adder Tree. applications,the flexibility of a filter with high-speed multipliers [2]is not necessary. 1.INTRODUCTION In this paper,we present a new high-speed,CSD coefficient FIR filter structure.Through studying CSD coefficient F inite Impulse response (FIR)filters have been used in filters,Booth multipliers and high-speed adders,we consumer electronics products more and more widely, propose a new programmable CSD encoding structure to such as video and communication circuits.Hence,higher make CSD coefficients programmable.With this structure, performance in speed and area is demanded.The traditional we can implement any order of high-speed FIR filters,and FIR filter structure [1],as shown in Fig.I,has not yet met the critical path is almost not proportional to the tap the high-speed demand of high performance systems number.In the following,we will respectively address CSD because of the limit of multiplier and adder circuits in speed encoding in FIR filters in the second part,programmable and area. CSD encoding structure in the third part and the structure of partial-product adder tree in the fourth part.In the end, The transform function of FIR filter is described by we adopt the presented structure to implement a 10-bits,18- taps video luminance filter. y(n)= h(k)x(n-k) (1) k=0 II.CSD ENCODING IN FIR FILTER The critical path of the FIR filter in Fig.I is TM+MTA,TM In many applications,coefficients are fixed in FIR filter. is the delay of one multiplication,TA is the delay of one Thus we can simply shift the data bus to the left or right by adder,and M is the tap number.It is evident that the critical an appropriate number of bits and employ a small number path is rapidly increasing with the tap number of FIR filter. of adders/subtracters instead of multipliers.The resulting hardware complexity is a small fraction of the complexity High-speed digital filtering applications (such as,sample of a general filter with multipliers and thus a significantly rates in excess of 20MHz)generally require the use of larger number of taps can be integrated into a single chip. custom application specific integrated circuits (ASICs), because programmable signal processors (such as DSPs) As we all know,any fraction can be described by [3]. This work is supported by AM (Applied Material)Funds (NO.0108)of X= -P shanghai,in P.R.China.Zhangwen Tang,Jie Zhang and Hao Min are with (2) ASIC Systern State-key Laboratory,Fudan University,220 Handan Road,Shanghai 200433,P.R.China. Contributed Paper Original manuscript received March 25,2001 Revised manuscript received May 16,2002 00983063/00$10.002002IEEE