D Cb A FIGURE 81.21 PROM logic circuit. Sequential Logic Circuits A sequential logic circuit is a circuit that has feedback such that the output signals of the circuit are functions of all or part of the present state output signals of the circuit in addition to any external input signals to the circuit. The vast majority of sequential logic circuits designed for industrial applications are synchronous or clock-mode circuits Synchronous Sequential Logic Circuits Synchronous sequential logic circuits change states only at the rising or falling edge of the smra logic circuit signal. To allow proper circuit operation, any external input signals to the synchronous sequent must generate excitation inputs that occur with the proper setup time(t,)and hold time(th) requirements relative to the designated clock edge for the memory elements being used. Synchronous or clock-mode sequen tial logic circuits depend on the present state of memory devices called bistables or flip-flops(asynchronou sequential logic circuits) that are driven by a system clock as illustrated by the synchronous sequential logic circuit in Fig. 81.23 with the availability of edge-triggered D flip-flops and edge-triggered J-Kflip-flops in IC packages, a designer can choose which flip-flop type to use as the memory devices in the memory section of a synchronous sequential logic circuit. Many designers prefer to design with edge-triggered D flip-flops rather than edge-triggered J-K p-flops because D flip-flops are (a)more cost efficient, (b) easier to design with, and(c) more convenient since many of the available Pal devices incorporate edge-triggered D flip-flops in the output section of their architectures. PAL devices that contain flip-flops in their output section are referred to as registered PALs(or, in general, registered PLDs). The synchronous sequential logic circuit shown in Fig. 81.24 using edge-triggered D flip-flops functionally performs the same as the circuit in Fig. 81.23. e 2000 by CRC Press LLC© 2000 by CRC Press LLC Sequential Logic Circuits A sequential logic circuit is a circuit that has feedback such that the output signals of the circuit are functions of all or part of the present state output signals of the circuit in addition to any external input signals to the circuit. The vast majority of sequential logic circuits designed for industrial applications are synchronous or clock-mode circuits. Synchronous Sequential Logic Circuits Synchronous sequential logic circuits change states only at the rising or falling edge of the synchronous clock signal. To allow proper circuit operation, any external input signals to the synchronous sequential logic circuit must generate excitation inputs that occur with the proper setup time (tsu) and hold time (th) requirements relative to the designated clock edge for the memory elements being used. Synchronous or clock-mode sequen￾tial logic circuits depend on the present state of memory devices called bistables or flip-flops (asynchronous sequential logic circuits) that are driven by a system clock as illustrated by the synchronous sequential logic circuit in Fig. 81.23. With the availability of edge-triggered D flip-flops and edge-triggered J-K flip-flops in IC packages, a designer can choose which flip-flop type to use as the memory devices in the memory section of a synchronous sequential logic circuit. Many designers prefer to design with edge-triggered D flip-flops rather than edge-triggered J-K flip-flops because D flip-flops are (a) more cost efficient, (b) easier to design with, and (c) more convenient since many of the available PAL devices incorporate edge-triggered D flip-flops in the output section of their architectures. PAL devices that contain flip-flops in their output section are referred to as registered PALs (or, in general, registered PLDs). The synchronous sequential logic circuit shown in Fig. 81.24 using edge-triggered D flip-flops functionally performs the same as the circuit in Fig. 81.23. FIGURE 81.21 PROM logic circuit