T ■T FIGURE 81.22 PALl6L8 implementation for the binary to seven-segment hexadecimal character generator. Source: PAL Device Data Book, Advanced Micro Devices, Sunnyvale, Calif, 1988, P. 5-46.) Notice that in general more combinational logic gates will be required for D flip-flop implementations ompared to J-K flip-flop implementations of the same synchronous sequential function. Using a registered PAL such as a PALI6RP4A would only require one IC package to implement the circuit in Fig. 81.24. The PAL16RP4A has four edge-triggered D flip-flops in its output section, of which only two are required for this design. Generally speaking, synchronous sequential logic circuits can be designed much more easily(considering design time as the criteria)than fundamental-mode asynchronous sequential logic circuits with a system clock and edge-triggered flip-flops, a designer does not have to worry about hazards or glitches(momentary error conditions that occur at the outputs of combinational logic circuits), since outputs are allowed to become stable before the next clock edge occurs. Thus, sequential logic circuit designs allow the use of combinational hazardou circuits as well as the use of arbitrary state assignments, provided the resulting combinational logic gate count e 2000 by CRC Press LLC© 2000 by CRC Press LLC Notice that in general more combinational logic gates will be required for D flip-flop implementations compared to J-K flip-flop implementations of the same synchronous sequential function. Using a registered PAL such as a PAL16RP4A would only require one IC package to implement the circuit in Fig. 81.24. The PAL16RP4A has four edge-triggered D flip-flops in its output section, of which only two are required for this design. Generally speaking, synchronous sequential logic circuits can be designed much more easily (considering design time as the criteria) than fundamental-mode asynchronous sequential logic circuits. With a system clock and edge-triggered flip-flops, a designer does not have to worry about hazards or glitches (momentary error conditions that occur at the outputs of combinational logic circuits), since outputs are allowed to become stable before the next clock edge occurs. Thus, sequential logic circuit designs allow the use of combinational hazardous circuits as well as the use of arbitrary state assignments, provided the resulting combinational logic gate count or package count is acceptable. FIGURE 81.22 PAL16L8 implementation for the binary to seven-segment hexadecimal character generator. (Source: PAL Device Data Book, Advanced Micro Devices, Sunnyvale, Calif., 1988, p. 5–46.)