DC FIGURE 81.23 Synchronous sequential logic circuit using positive edge-triggered J-K flip-flo DC y1 y2 HC FIGURE 81.24 Synchronous sequential logic circuit using positive edge-triggered D flip-flops. IEEE symbol FIGURE 81.25 Fundamental-mode asynchronous sequential logic circuit. Asynchronous Sequential Logic Circuits Asynchronous sequential logic circuits may change states any time a single input signal occurs(either a level change for a fundamental mode circuit or a pulse for a pulse mode circuit). No other input signal change (either level change or pulse) is allowed until the circuit reaches a stable internal state. Latches and edge triggered flip-flops are asynchronous sequential logic circuits and must be designed with care by utilizing hazard-free combinational logic circuits and race-free or critical race-free state assignments. Both hazards and race conditions interfere with the proper operation of asynchronous logic circuits. The gated D latch circuit e 2000 by CRC Press LLC© 2000 by CRC Press LLC Asynchronous Sequential Logic Circuits Asynchronous sequential logic circuits may change states any time a single input signal occurs (either a level change for a fundamental mode circuit or a pulse for a pulse mode circuit). No other input signal change (either level change or pulse) is allowed until the circuit reaches a stable internal state. Latches and edge￾triggered flip-flops are asynchronous sequential logic circuits and must be designed with care by utilizing hazard-free combinational logic circuits and race-free or critical race-free state assignments. Both hazards and race conditions interfere with the proper operation of asynchronous logic circuits. The gated D latch circuit FIGURE 81.23 Synchronous sequential logic circuit using positive edge-triggered J-K flip-flops. FIGURE 81.24 Synchronous sequential logic circuit using positive edge-triggered D flip-flops. FIGURE 81.25 Fundamental-mode asynchronous sequential logic circuit