FIGURE 81.26 Double- rank pulse- mode asynchronous sequential logic circuit lustrated in Fig. 81.25 is an example of a fundamental-mode asynchronous sequential logic circuit that is used extensively in microprocessor systems for the temporary storage of data Quad, octal, 9-bit, and 10-bit transparent latches are readily available as off-the-shelf IC devices for these types of applications For proper asynchronous circuit operation, the signal applied to the data input D of the fundamental-mode circuit in Fig. 81.25 must meet a minimum setup time and hold time requirement relative he control input C, changing the latch to the memory mode when C goes to 0. This is a basic requirement for asynchronous circuits with level inputs, i.e., only one input signal is allowed to change at one time. Another restriction requires letting the circuit reach a stable state before allowing the next input signal to change An example of a reliable pulse-mode asynchronous sequential logic circuit is shown in Fig. 81. 26. While the inputs to asynchronous fundamental-mode circuits are logic levels, the inputs to asynchronous pulse-mode circuits are pulses. Pulse-mode circuits have the restriction that the maximum pulse width of any input pulse must be sufficiently narrow such that an input pulse is no longer present when the new present state output signal becomes available. The purpose of the double-rank circuit in Fig. 81. 26 is to ensure that the maximum pulse width requirement is easily met, since the output is not fed back until the input pulse is removed, i.e Des low or goes to logic 0. The input signals to pulse-mode circuits must also meet the following res strictions only one input pulse may be applied at one time, (b)the circuit must be allowed to reach a new stable state before applying the next input pulse, and (c) the minimum pulse width of an input pulse is determined by the time it takes to change the slowest flip-flop used in the circuit to a new stable state Defining Terms Asynchronous circuit: A sequential logic circuit without a system clock. Combinational logic circuit: A circuit with external output signal(s)that are totally dependent on the external input signals applied to the circuit. Fan-out requirement: The maximum number of loads a device output can drive and still provide dependable I and 0 logic levels Hazard or glitch: A momentary output error that occurs in a logic circuit because of input signal propagation along different delay paths in the circuit. Hexadecimal: The name of the number system with a base or radix of 16 with the usual symbols of 0 9,A, B,C,, F. Medium-scale integration: A single packaged IC device with 12 to 99 gate-equivalent circuits Race-free state assignment: A state assignment made for asynchronous sequential logic circuits such that nore than a one-bit change occurs between each stable state transition, thus preventing possible critical races. Sequential logic circuit: A circuit with output signals that are dependent on all or part of the present state ut signals fed back as input signals as well as any external input signals if they should exist. Sum of products(SOP): A standard form for writing a Boolean equation that contains product terms(input rariables or signal names either complemented or uncomplemented ANDed together)that are logically summed(ORed together ). Synchronous or clock -mode circuit: A sequential logic circuit that is synchronized with a system clock. e 2000 by CRC Press LLC© 2000 by CRC Press LLC illustrated in Fig. 81.25 is an example of a fundamental-mode asynchronous sequential logic circuit that is used extensively in microprocessor systems for the temporary storage of data. Quad, octal, 9-bit, and 10-bit transparent latches are readily available as off-the-shelf IC devices for these types of applications. For proper asynchronous circuit operation, the signal applied to the data input D of the fundamental-mode circuit in Fig. 81.25 must meet a minimum setup time and hold time requirement relative to the control input C, changing the latch to the memory mode when C goes to 0. This is a basic requirement for asynchronous circuits with level inputs, i.e., only one input signal is allowed to change at one time. Another restriction requires letting the circuit reach a stable state before allowing the next input signal to change. An example of a reliable pulse-mode asynchronous sequential logic circuit is shown in Fig. 81.26. While the inputs to asynchronous fundamental-mode circuits are logic levels, the inputs to asynchronous pulse-mode circuits are pulses. Pulse-mode circuits have the restriction that the maximum pulse width of any input pulse must be sufficiently narrow such that an input pulse is no longer present when the new present state output signal becomes available. The purpose of the double-rank circuit in Fig. 81.26 is to ensure that the maximum pulse width requirement is easily met, since the output is not fed back until the input pulse is removed, i.e., goes low or goes to logic 0. The input signals to pulse-mode circuits must also meet the following restrictions: (a) only one input pulse may be applied at one time, (b) the circuit must be allowed to reach a new stable state before applying the next input pulse, and (c) the minimum pulse width of an input pulse is determined by the time it takes to change the slowest flip-flop used in the circuit to a new stable state. Defining Terms Asynchronous circuit: A sequential logic circuit without a system clock. Combinational logic circuit: A circuit with external output signal(s) that are totally dependent on the external input signals applied to the circuit. Fan-out requirement: The maximum number of loads a device output can drive and still provide dependable 1 and 0 logic levels. Hazard or glitch: A momentary output error that occurs in a logic circuit because of input signal propagation along different delay paths in the circuit. Hexadecimal: The name of the number system with a base or radix of 16 with the usual symbols of 0 … 9,A,B,C,D,E,F. Medium-scale integration: A single packaged IC device with 12 to 99 gate-equivalent circuits. Race-free state assignment: A state assignment made for asynchronous sequential logic circuits such that no more than a one-bit change occurs between each stable state transition, thus preventing possible critical races. Sequential logic circuit: A circuit with output signals that are dependent on all or part of the present state output signals fed back as input signals as well as any external input signals if they should exist. Sum of products (SOP): A standard form for writing a Boolean equation that contains product terms (input variables or signal names either complemented or uncomplemented ANDed together) that are logically summed (ORed together). Synchronous or clock-mode circuit: A sequential logic circuit that is synchronized with a system clock. FIGURE 81.26 Double-rank pulse-mode asynchronous sequential logic circuit