State Machine Design .Design a state machine that will detect a Serial pattern of 011011 from a serial in stream .When this pattern is detected set match=output for one cycle Test your design by Input the following pattern“011101”,“011011” Serial in VHDL State Match Machine clk Copyright 1997 Altera Corporation 2/22/2021P2 favaraCopyright © 1997 Altera Corporation 2/22/2021 P.2 State Machine Design •Design a state machine that will detect a Serial pattern of “011011” from a serial_in stream •When this pattern is detected set match = ‘1’ output for one cycle •Test your design by Input the following pattern “011101”, “011011” Serial_in Match clk VHDL State Machine