Table 2 shows modified one-hot state assi ished bthetateCreatemofied ersion of your VHDL that implemnt this state assignment.Hint:you should need to make very few changes to the logic expressions in you d codes.Compile your new circuit and test it both through simulation and State code Name ysy7654s2h 0000 00000101 000001001 00001000 00I000 010000001 100000001 Table 2.Modified one-hot codes for the FSM. Part For this part you are to write another style of VHDL code for the FSM in Figure 2.In this version of the code you should not manually derive the logic expressions needed for each state flip-flop.Instead,describe the state table for the inantiate theaeYou c ROCESS block or imple ment statemenstopi the FSM b ESS block,and use another PROCESS block t Asuggested skeleton of the VHDL code is given in Figure 3.Observe that the present and next state vectors for the FSM are defined as an enumerated type with possible values given by the symbols A to I.The VHDL compiler determines how many state flip-flops to use for the circuit,and it automatically chooses the state assignment Table 2 shows a modified one-hot state assignment in which the reset state, A, uses all 0s. This is accom￾plished by inverting the state variable y0. Create a modified version of your VHDL code that implements this state assignment. Hint: you should need to make very few changes to the logic expressions in your circuit to implement the modified codes. Compile your new circuit and test it both through simulation and by downloading it onto the DE2 board. State Code Name y8y7y6y5y4y3y2y1y0 A 000000000 B 000000011 C 000000101 D 000001001 E 000010001 F 000100001 G 001000001 H 010000001 I 100000001 Table 2. Modified one-hot codes for the FSM. Part II For this part you are to write another style of VHDL code for the FSM in Figure 2. In this version of the code you should not manually derive the logic expressions needed for each state flip-flop. Instead, describe the state table for the FSM by using a VHDL CASE statement in a PROCESS block, and use another PROCESS block to instantiate the state flip-flops. You can use a third PROCESS block or simple assignment statements to specify the output z. A suggested skeleton of the VHDL code is given in Figure 3. Observe that the present and next state vectors for the FSM are defined as an enumerated type with possible values given by the symbols A to I. The VHDL compiler determines how many state flip-flops to use for the circuit, and it automatically chooses the state assignment. 3