Typical Architecture for RTS USTC 嵌入式系统虽然复杂，但通用处理器的设计经验会有很大帮助 Peripheral Bus DEBUG Port Non-volatile memory Custom Devices ·EPROM,FLASH,DISK ·ASIC Hybrid ·FPGA Microprocessor ·PAL 4.8.16.32.4 bit bus ·CISc,RISC,DSP Standard Devices Integrated peripherals Volatile Memory ·Debug/Test Port 1/0 Ports ·DRAM,SRAM ·Caches Peripheral Controllers ·Pipeline Hybrid Multiprocessing Systems Communication Devices ·Ethemet .RS-232 ·scsl ·Centronics System Clocks Proprietary RTC circuitry Software ·System clocks ·Application Code Integrated in uC ·Driver Code/BIOS ·Imported/Exported Microprocessor Bus Real Time Operating System ·Custom User Interface ·PCI Communications Protocol Stacks ·VME .C.C++,Assembly Language ·P℃-102 ·Legacy Code llxx@ustc.edu.cn 5/87Typical Architecture for RTS llxx@ustc.edu.cn 5/87