IMPLEMENTATION OF PAGE TABLE o Page table is kept in main memory o Page-table base register(PTBR)points to the page table o Page-table length register (PRLR)indicates size of the page table o In this scheme every data/instruction access requires two memory accesses.One for the page table and one for the data/instruction. o The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) 0 Some TLBs store address-space identifiers (ASIDs)in each TLB entry-uniquely identifies each process to provide address-space protection for that processIMPLEMENTATION OF PAGE TABLE  Page table is kept in main memory  Page-table base register (PTBR) points to the page table  Page-table length register (PRLR) indicates size of the page table  In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction.  The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs)  Some TLBs store address-space identifiers (ASIDs) in each TLB entry – uniquely identifies each process to provide address-space protection for that process