VHDL中的结构设计的实例 begin ul: kiny port map(n(3), n3 D; u2: kin port map(n(2), n2 D; u3: kiny port map(n(1), nl D; u4: kand2 port map(n3 L, n(0), n31 n0) u5: kand3 port map(n3 L, n2 L,n(1), n31 n2I nD); u6: kand3 port map(n2 L,n(1), n(0), n2l n1 n0); u7: kand3 port map(n(2), nl l, n(0), n2 n1l nO); u8: kor 4 port map (n3l n0, n31 n21 nl, n2I nl n0, n2 nll no, f end prime arch;VHDL中的结构设计的实例 begin u1: kinv port map (n(3),n3_l); u2: kinv port map (n(2),n2_l); u3: kinv port map (n(1),n1_l); u4: kand2 port map (n3_l,n(0),n3l_n0); u5: kand3 port map (n3_l,n2_l,n(1),n3l_n2l_n1); u6: kand3 port map (n2_l,n(1),n(0),n2l_n1_n0); u7: kand3 port map (n(2),n1_l,n(0),n2_n1l_n0); u8: kor4 port map (n3l_n0,n3l_n2l_n1,n2l_n1_n0,n2_n1l_n0,f); end prime1_arch;