VHDL中的结构设计的实例 质数检测器的结构设计p284表4-43 architecture prime arch of prime is signal n3 Ln2 L, nl l:std logic; signal n31 n0, n31 n2I n1, n2l n1 n0 n2 nll nO: std logic; component kinv port(a: in std logic; y: out std logic);end component; component kand2 port(a0, al: in std logic;y: out std logic);end component; component kand port(a0, al, a2: in std logic;y: out std logic);end component; component kor4 port(a0, al, a2, a3: in std logic; y: out std logic);end componentVHDL中的结构设计的实例 质数检测器的结构设计p.284 表4-43 architecture prime1_arch of prime is signal n3_l,n2_l,n1_l:std_logic; signal n3l_n0,n3l_n2l_n1,n2l_n1_n0 ,n2_n1l_n0:std_logic; component kinv port (a: in std_logic;y: out std_logic);end component; component kand2 port (a0,a1: in std_logic;y: out std_logic);end component; component kand3 port (a0,a1,a2: in std_logic;y: out std_logic);end component; component kor4 port (a0,a1,a2,a3: in std_logic;y: out std_logic);end component;