ARCHITECTURE variable delay Of and2 gate IS CONSTANT Tplh typ: time: =5 ns CONSTANT Tphl typ: time: =8ns BEGIN and inputs PROCESS (inO, in1) BEGIN IF (inO AND in1)=I' THEN outl<=1 AFTER Tplh typ ELSIF (inO AND in1)=0 THEN outl<=0 AFTER Tphl typ ELSIF ( Tph typ >=Tphl typ)THEN outl <=X AFTER TpIh typ ELSE outl<=X AFTER TphI typ END IF END PROCESS and inputs, END variable delayARCHITECTURE variable_delay OF and2_gate IS CONSTANT Tplh_typ : time := 5 ns; CONSTANT Tphl_typ : time := 8 ns; BEGIN and_inputs : PROCESS (in0, in1) BEGIN IF (in0 AND in1) = ‘1’ THEN out1 <= ‘1’ AFTER Tplh_typ; ELSIF (in0 AND in1) = ‘0’ THEN out1 <= ‘0’ AFTER Tphl_typ; ELSIF (Tplh_typ >= Tphl_typ) THEN out1 <= ‘X’ AFTER Tplh_typ; ELSE out1 <= ‘X’ AFTER Tphl_typ; END IF; END PROCESS and_inputs; END variable_delay;