155J/6.152JFal2003 MOSCAP MOSCAP LAB SESSION 3 Photolithography and Gate Patterning Location: ICL (2 floor, Building 39) Overview of lab session In this lab session, photolithography will be used to transfer an image from a mask to the wafer Wafers will be coated with photoresist on the sSI track, similar to the photoresist application step in Lab Session 2, except that wafers will be pre-baked. The pattern will be transferred from a mask to the wafer using the Nikon NSR2005i9 Wafer Stepper( i-stepper), a projection aligner The photoresist in the clear fields of the mask is exposed to UV light, and resist in these areas is removed when the wafer is developed. Finally, the wafer is post-baked to improve adhesion Using the photoresist as an etch mask, the polysilicon will be dry-etched using He/Cl2 plasma After this step, the photoresist will be ashed, and the process is completed Lab objectives Introduction to photolithographic process and procedures Patterning of polysilicon gate electrode Instruction on the following pieces of equipment SSI Coater Track Nikon NSR2005i9 Wafer Stepper(i-stepper LAM 490B Plasma Etcher Matrix 106 System One Stripper Optical Microscope Before attending this lab session, make sure to read the Standard Operating Procedures for the above equipment. SOPs can be accessed at: http://www-mtl.mitedw/mtihome/3mfab/sop.html ab procedures. 1. HMDS, photoresist depostion, and pre-bake Follow the SOP for the SSI Coater Track, using the following modules In-line HMDs treatment Spin-on module: standard dispense for -1 micron thickness Pre-bake module: 95c on hot plate 2. Exposure, development and inspection Refer to Appendix for mask schematics Use the l-stepper to transfer mask pattern to wafers Use control wafer to make a'focus-expo' grid-a matrix of various focal lengths and Develop this wafer using the following modules of the SSI Coater Track Post-exposure bake Develop Post-bake Inspect developed control wafer with optical microscope and determine optimal focal length and exposure time Use these settings for exposure of device wafers Develop device wafers using the following modules of the SSl Coater Track Post-exposure bake Develop Postbake Inspect wafers visually with optical microscope3.155J / 6.152J Fall 2003 MOSCAP 6 MOSCAP LAB SESSION 3 Photolithography and Gate Patterning Location: ICL (2nd floor, Building 39) Overview of Lab Session: In this lab session, photolithography will be used to transfer an image from a mask to the wafer. Wafers will be coated with photoresist on the SSI track, similar to the photoresist application step in Lab Session 2, except that wafers will be pre-baked. The pattern will be transferred from a mask to the wafer using the Nikon NSR2005i9 Wafer Stepper (i-stepper), a projection aligner. The photoresist in the clear fields of the mask is exposed to UV light, and resist in these areas is removed when the wafer is developed. Finally, the wafer is post-baked to improve adhesion. Using the photoresist as an etch mask, the polysilicon will be dry-etched using He/Cl2 plasma. After this step, the photoresist will be ashed, and the process is completed. Lab Objectives: • Introduction to photolithographic process and procedures. • Patterning of polysilicon gate electrode. • Instruction on the following pieces of equipment: • SSI Coater Track • Nikon NSR2005i9 Wafer Stepper (i-stepper) • LAM 490B Plasma Etcher. • Matrix 106 System One Stripper • Optical Microscope Before attending this lab session, make sure to read the Standard Operating Procedures for the above equipment. SOPs can be accessed at: http://www-mtl.mit.edu/mtlhome/3Mfab/sop.html Lab Procedures: 1. HMDS, photoresist depostion, and pre-bake. Follow the SOP for the SSI Coater Track, using the following modules: • In-line HMDS treatment • Spin-on module: standard dispense for ~1 micron thickness • Pre-bake module: 95 C on hot plate. 2. Exposure, development and inspection Refer to Appendix for mask schematics. Use the I-stepper to transfer mask pattern to wafers. • Use control wafer to make a ‘focus-expo’ grid --- a matrix of various focal lengths and exposure times. • Develop this wafer using the following modules of the SSI Coater Track: ƒ Post-exposure bake ƒ Develop ƒ Post-bake • Inspect developed control wafer with optical microscope and determine optimal focal length and exposure time. • Use these settings for exposure of device wafers . • Develop device wafers using the following modules of the SSI Coater Track: ƒ Post-exposure bake ƒ Develop ƒ Postbake • Inspect wafers visually with optical microscope