CONTENTS xiii 15.4.3 Duan's Switch 505 15.4.43 M Switch/506 15.5 Optical Packet Switch with Shared Fiber Delay Lines Single-stage Case 509 15.5.1 Optical Cell Switch Architecture 509 15.5.2 Sequential FDL Assignment(SEFA)Algorithm /512 15.5.3 Multi-Cell FDL Assignment(MUFA)Algorithm /518 15.6 All Optical Packet Switch with Shared Fiber Delay Lines-Three Stage Case 524 15.6.1 Sequential FDL Assignment for Three-Stage OCNS(SEFAC)/526 15.6.2 Multi-Cell FDL Assignment for Three-Stage OCNS(MUFAC)/526 15.6.3 FDL Distribution in Three-Stage OCNS /528 15.6.4 Performance Analysis of SEFAC and MUFAC 530 15.6.5 Complexity Analysis of SEFAC and MUFAC 532 16 HIGH-SPEED ROUTER CHIP SET 538 16.1 Network Processors(NPs)/538 16.1.1 Overview /538 16.1.2 Design Issues for Network Processors /539 16.1.3 Architecture of Network Processors 542 16.1.4 Examples of Network Processors-Dedicated Approach /543 16.2 Co-Processors for Packet Classification 554 16.2.1LA-1Bus/554 16.2.2 TCAM-Based Classification Co-Processor 556 16.2.3 Algorithm-Based Classification Co-Processor /562 16.3 Traffic Management Chips 567 16.3.1 Overview /567 16.3.2 Agere's TM Chip Set 567 16.3.3 IDT TM Chip Set 573 16.3.4 Summary /579 16.4 Switching Fabric Chips /579 16.4.1 Overview /579 16.4.2 Switch Fabric Chip Set from Vitesse /580 16.4.3 Switch Fabric Chip Set from AMCC 589 16.4.4 Switch Fabric Chip Set from IBM(now of AMCC)/593 16.4.5 Switch Fabric Chip Set from Agere /597 INDEX 606Book1099 — “ftoc” — 2007/2/16 — 21:26 — page xiii — #9 CONTENTS xiii 15.4.3 Duan’s Switch / 505 15.4.4 3M Switch / 506 15.5 Optical Packet Switch with Shared Fiber Delay Lines Single-stage Case / 509 15.5.1 Optical Cell Switch Architecture / 509 15.5.2 Sequential FDL Assignment (SEFA) Algorithm / 512 15.5.3 Multi-Cell FDL Assignment (MUFA) Algorithm / 518 15.6 All Optical Packet Switch with Shared Fiber Delay Lines – Three Stage Case / 524 15.6.1 Sequential FDL Assignment for Three-Stage OCNS (SEFAC) / 526 15.6.2 Multi-Cell FDL Assignment for Three-Stage OCNS (MUFAC) / 526 15.6.3 FDL Distribution in Three-Stage OCNS / 528 15.6.4 Performance Analysis of SEFAC and MUFAC / 530 15.6.5 Complexity Analysis of SEFAC and MUFAC / 532 16 HIGH-SPEED ROUTER CHIP SET 538 16.1 Network Processors (NPs) / 538 16.1.1 Overview / 538 16.1.2 Design Issues for Network Processors / 539 16.1.3 Architecture of Network Processors / 542 16.1.4 Examples of Network Processors – Dedicated Approach / 543 16.2 Co-Processors for Packet Classification / 554 16.2.1 LA-1 Bus / 554 16.2.2 TCAM-Based Classification Co-Processor / 556 16.2.3 Algorithm-Based Classification Co-Processor / 562 16.3 Traffic Management Chips / 567 16.3.1 Overview / 567 16.3.2 Agere’s TM Chip Set / 567 16.3.3 IDT TM Chip Set / 573 16.3.4 Summary / 579 16.4 Switching Fabric Chips / 579 16.4.1 Overview / 579 16.4.2 Switch Fabric Chip Set from Vitesse / 580 16.4.3 Switch Fabric Chip Set from AMCC / 589 16.4.4 Switch Fabric Chip Set from IBM (now of AMCC) / 593 16.4.5 Switch Fabric Chip Set from Agere / 597 INDEX 606