ON MT9P31:1/25-Inch5Mp Serial Bus Description al interface slave a s contro d by chip by a 1.5k resistor.Either the slave or master device can pull the SDATA line LOW- the serial interface protocol determines which device is allowed to pull the SDATA line down at any given time Protocol The two-wire serial defines several different transmission codes,as follows: 1.astart bit 2.the slave device 8-bit address 3.an(a no)acknowledge bit 4.an 8-bit message 5.a stop bit Sequence ding a start bit. READ r a WRITE.whe s a WRITE and a“1" indicates a READ.The slave device acknowledges its address by sending an acknowledge bit back to the master. eteeiaa心RIethmiterthermncrohe&g f the tis a WRITE th he &.hit which a register address has been received.The master then transfers the data 8 bits at a time with the slave sending an acknowledge bit after each 8 bits.The MT9P031 uses 16-bit data for interal registers.thusr equing two oit transters to write to on e register sending a start or stop bit. typical READ ed as s.First the ster sends the write-n register data 8 bits at a time.The master sends an acknowledge bit after each 8-bit trans en th e master sends edge Bus Idle State The bus is idle when both the data and clock lines are HIGH.Control of the bus is initi- ated with a start bit,and the bus is released with a stop bit.Only the master can generate the start and stop bits Start Bit The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line isHIGH.MT9P031_DS Rev. J 5/15 EN 17 ©Semiconductor Components Industries, LLC,2015. MT9P031: 1/2.5-Inch 5 Mp Digital Image Sensor Serial Bus Description Serial Bus Description Registers are written to and read from the MT9P031 through the two-wire serial interface bus. The MT9P031 is a serial interface slave and is controlled by the serial clock (SCLK), which is driven by the serial interface master. Data is transferred into and out of the MT9P031 through the serial data (SDATA) line. The SDATA line is pulled up to VDD_IO off￾chip by a 1.5k resistor. Either the slave or master device can pull the SDATA line LOW— the serial interface protocol determines which device is allowed to pull the SDATA line down at any given time. Protocol The two-wire serial defines several different transmission codes, as follows: 1. a start bit 2. the slave device 8-bit address 3. an (a no) acknowledge bit 4. an 8-bit message 5. a stop bit Sequence A typical READ or WRITE sequence begins by the master sending a start bit. After the start bit, the master sends the slave device's 8-bit address. The last bit of the address determines if the request is a READ or a WRITE, where a “0” indicates a WRITE and a “1” indicates a READ. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request is a WRITE, the master then transfers the 8-bit register address to which a WRITE should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data 8 bits at a time, with the slave sending an acknowledge bit after each 8 bits. The MT9P031 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical READ sequence is executed as follows. First the master sends the write-mode slave address and 8-bit register address, just as in the WRITE request. The master then sends a start bit and the read-mode slave address. The master then clocks out the register data 8 bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register address is automatically-incremented after every 16 bits is trans￾ferred. The data transfer is stopped when the master sends a no-acknowledge bit. Bus Idle State The bus is idle when both the data and clock lines are HIGH. Control of the bus is initi￾ated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits. Start Bit The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH